Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

J. Guarracini

dblp:180/6466 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 1965
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 67% Emerging computing paradigms · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms › neuromorphic computing
associative memory
0.011965
Fixed Resistor-Card Memory · IEEE Trans. Electron. Comput. 1965
Memory systems
content-addressable memory
0.011965
Fixed Resistor-Card Memory · IEEE Trans. Electron. Comput. 1965
Memory systems › non-volatile memory
read-only memory
0.011965
Fixed Resistor-Card Memory · IEEE Trans. Electron. Comput. 1965
YearPublicationVenuePosition
1965 Fixed Resistor-Card Memory
abstract
A fixed or read-only memory, consisting of a stack of paper or plastic punched cards, each containing an interconnected array of printed resistors, is discussed. The cards are compatible with conventional keypunches, and information is recorded on each card by the punching of a pattern of holes, each of which severs an appropriate connection. An interconnection method, which involves the injection of molten, low-temperature solder alloy into special channels in the stack, is described. This technique provides all card- to-card interconnections simultaneously. It is shown that the memory can be operated in a content-addressable or associative mode. Experimental results, dealing with resistor silk-screening and card stack construction and operation, are presented.
Morton H. Lewin, H. R. Beelitz, J. Guarracini
IEEE Trans. Electron. Comput.3