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H. H. Harris Jr.

dblp:180/6525 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1964
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
delay-line memory		 0.011964
Tunnel Diode Delay-Line Memory · IEEE Trans. Electron. Comput. 1964
Memory systems › memory architecture
serial memory		 0.011964
Tunnel Diode Delay-Line Memory · IEEE Trans. Electron. Comput. 1964

Methods — techniques the papers use, named apart from their topics

simulation · 0.0
YearPublicationVenuePosition
1964 Tunnel Diode Delay-Line Memory
abstract
This paper describes a memory system wherein bits of information are stored serially in time on electrical delay lines, The simplicity and speed of the basic storage cell makes large high-speed stores of this sort feasible. The paper stresses the basic principles of operation. A brief description of one such system model built to demonstrate these principles is included.
H. H. Harris Jr., W. David Pricer
 IEEE Trans. Electron. Comput.1