Modern Field Programmable Gate Arrays (FPGAs) are large-scale heterogeneous programmable devices that enable high performance and energy efficiency. Placement is a crucial and computationally intensive step in the FPGA design flow that determines the physical locations of various heterogeneous instances in the design. Several works have employed GPUs and FPGAs to accelerate FPGA placement and have obtained significant runtime improvement. However, with these approaches, it is a non-trivial effort to develop optimized and algorithmic-specific kernels for GPU and FPGA to realize the best acceleration performance. In this work, we present DREAMPlaceFPGA, an open-source deep-learning toolkit-based accelerated placement framework for large-scale heterogeneous FPGAs. Notably, we develop new operators in our framework to handle heterogeneous resources and FPGA architecture-specific legality constraints. The proposed framework requires low development cost and provides an extensible framework to employ different placement optimizations. Our experimental results on the ISPD'2016 benchmarks show very promising results compared to prior approaches.

As the integrated circuits (ICs) technology continues to scale, resolution enhancement techniques (RETs) are mandatory to obtain high manufacturing quality and yield. Among various RETs, subresolution assist feature (SRAF) generation is a key technique to improve the target pattern quality and lithographic process window. While model-based SRAF insertion techniques have demonstrated high accuracy, they usually suffer from high computational cost. Therefore, more efficient techniques that can achieve high accuracy while reducing runtime are in strong demand. In this article, we leverage the recent advancement in machine learning for image generation to tackle the SRAF insertion problem. In particular, we propose a new SRAF insertion framework, GAN-SRAF, which uses generative adversarial networks (GANs) to generate SRAFs directly for any given layout. Our proposed approach incorporates a novel layout to image encoding using multichannel heatmaps to preserve the layout information and facilitate layout reconstruction. Our experimental results demonstrate ~14.6× reduction in runtime when compared to the previous best machine learning approach for SRAF generation, and ~144× reduction compared to the model-based approach, while achieving comparable quality of results.

To speed up the FPGA placement and routing closure, we propose a novel approach to predict the routing congestion map for large-scale FPGA designs at the placement stage. After reformulating the problem into an image translation task, our proposed approach leverages recent advancement in generative adversarial learning to address the task. Particularly, state-of-the-art generative adversarial networks for high-resolution image translation are used along with well-engineered features extracted from the placement stage. Unlike available approaches, our novel framework demonstrates a capability of handling large-scale FPGA designs. With its superior accuracy, our proposed approach can be incorporated into the placement engine to provide congestion prediction resulting in up to 7% reduction in routed wirelength for the most congested design in ISPD 2016 benchmark.

With the continuous drive toward integrated circuits scaling, efficient yield analysis is becoming more crucial yet more challenging. In this paper, we propose a novel methodology for wafer map defect pattern classification using deep selective learning. Our proposed approach features an integrated reject option where the model chooses to abstain from predicting a class label when misclassification risk is high. Thus, providing a trade-off between prediction coverage and misclassification risk. This selective learning scheme allows for new defect class detection, concept shift detection, and resource allocation. Besides, and to address the class imbalance problem in the wafer map classification, we propose a data augmentation framework built around a convolutional auto-encoder model for synthetic sample generation. The efficacy of our proposed approach is demonstrated on the WM-811k industrial dataset where it achieves 94% accuracy under full coverage and 99% with selective learning while successfully detecting new defect types.

The continued scaling of integrated circuit technologies, along with the increased design complexity, has exacerbated the challenges associated with manufacturability and yield. In today's semiconductor manufacturing, lithography plays a fundamental role in printing design patterns on silicon. However, the growing complexity and variation of the manufacturing process have tremendously increased the lithography modeling and simulation cost. Besides, both the role and cost of resolution enhancement techniques (RETs) - now indispensable in the design process - have increased. Parallel to these developments are the recent advancements in Machine Learning (ML) which have provided a far-reaching data-driven perspective for problem solving. In this work, we shed light on the recent Deep Learning (DL) based approaches that have provided a new lens to examine traditional manufacturability and yield challenges. We present lithography modeling and simulation techniques, leveraging advanced learning paradigms, which have demonstrated unprecedented efficiency. Moreover, we demonstrate the role DL can play in advancing RETs by presenting its successful application in assist feature generation. Also critical to yield is the post fabrication wafer map defect analysis step which our work tackles using a novel confidence-aware deep learning scheme. This paper further discusses the future prospects of DL-based approaches in the scope of circuits manufacturability and yield.

With the continuous shrinking of the semiconductor device dimensions, mask topography effects stand out among the major factors influencing the lithography process. Including these effects in the lithography optimization procedure has become necessary for advanced technology nodes. However, conventional rigorous simulation for mask topography effects is extremely computationally expensive for high accuracy. In this work, we propose TEMPO as a novel generative learning-based framework for efficient and accurate 3D aerial image prediction. At its core, TEMPO comprises a generative adversarial network capable of predicting aerial image intensity at different resist heights. Compared to the default approach of building a unique model for each desired height, TEMPO takes as one of its inputs the desired height to produce the corresponding aerial image. In this way, the global model in TEMPO can capture the shared behavior among different heights, thus, resulting in smaller model size. Besides, across-height information sharing results in better model accuracy and generalization capability. Our experimental results demonstrate that TEMPO can obtain up to 1170x speedup compared with rigorous simulation while achieving satisfactory accuracy.

As integrated circuit technologies continue to scale, variability modeling is becoming more crucial yet, more challenging. In this paper, we propose a novel performance modeling method based on semi-supervised co-learning. We exploit the multiple representations of process variation in any analog and mixed signal circuit to establish a co-learning framework where unlabeled samples are leveraged to improve the model accuracy without enduring any simulation cost. Practically, our proposed method relies on a small set of labeled data, and the availability of no-cost unlabeled data to efficiently build accurate performance model for any analog and mixed signals circuit design. Our numerical experiments demonstrate that the proposed approach achieves up to 30% reduction in simulation cost compared to the state-of-the-art modeling technique without surrendering any accuracy.

With the continuous scaling of integrated circuit (IC) technologies, electromigration (EM) prevails as one of the major reliability challenges facing the design of robust circuits. With such aggressive scaling in advanced technology nodes, signal nets experience high switching frequency, which further exacerbates the signal EM effect. Traditionally, signal EM fixing approaches analyze EM violations after the routing stage and repair is attempted via iterative incremental routing or cell resizing techniques. However, these "EM-analysis-then fix" approaches are ill-equipped when faced with the ever-growing EM violations in advanced technology nodes. In this work, we propose a novel signal EM handling framework that (i) incorporates EM detection and fixing techniques into earlier stages of the physical design process, and (ii) integrates machine learning based detection alongside a multistage mitigation. Experimental results demonstrate that our framework can achieve 15x speedup when compared to the state-of-the-art EDA tool while achieving similar performance in terms of EM mitigation and overhead.

As the integrated circuits (IC) technology continues to scale, resolution enhancement techniques (RETs) are mandatory to obtain high manufacturing quality and yield. Among various RETs, sub-resolution assist feature (SRAF) generation is a key technique to improve the target pattern quality and lithographic process window. While model-based SRAF insertion techniques have demonstrated high accuracy, they usually suffer from high computational cost. Therefore, more efficient techniques that can achieve high accuracy while reducing runtime are in strong demand. In this work, we leverage the recent advancement in machine learning for image generation to tackle the SRAF insertion problem. In particular, we propose a new SRAF insertion framework, GAN-SRAF, which uses conditional generative adversarial networks (CGANs) to generate SRAFs directly for any given layout. Our proposed approach incorporates a novel layout to image encoding using multi-channel heatmaps to preserve the layout information and facilitate layout reconstruction. Our experimental results demonstrate ~14.6× reduction in runtime when compared to the previous best machine learning approach for SRAF generation, and ~144× reduction compared to model-based approach, while achieving comparable quality of results.

As integrated circuit technologies continue to scale, efficient performance modeling becomes indispensable. Recently, several new learning paradigms have been proposed to reduce the computational cost associated with accurate performance modeling. A common attribute among most of these paradigms is the leverage of the sparsity feature to build efficient performance models. In this work, we propose a new perspective to incorporate sparsity in the modeling task by utilizing spike and slab feature selection techniques. Practically, our proposed method uses two different priors on the different model coefficients based on their importance. This is incorporated into a mixture model that can be built using a hierarchical Bayesian framework to select the important features and find the model coefficients. Our numerical experiments demonstrate that the proposed approach can achieve better results compared to traditional sparse modeling techniques while also providing valuable insight about the important features in the model.

Lithography simulation is one of the most fundamental steps in process modeling and physical verification. Conventional simulation methods suffer from a tremendous computational cost for achieving high accuracy. Recently, machine learning was introduced to trade off between accuracy and runtime through speeding up the resist modeling stage of the simulation flow. In this work, we propose LithoGAN, an end-to-end lithography modeling framework based on a generative adversarial network (GAN), to map the input mask patterns directly to the output resist patterns. Our experimental results show that LithoGAN can predict resist patterns with high accuracy while achieving orders of magnitude speedup compared to conventional lithography simulation and previous machine learning based approach.

Lithography hotspot detection is one of the fundamental steps in physical verification. Due to the increasingly complicated design patterns, early and quick feedback for lithography hotspots is desired to guide design closure in early stages. Machine learning approaches have been successfully applied to hotspot detection while demonstrating a remarkable capability of generalization to unseen hotspot patterns. However, most of the proposed machine learning approaches are not yet able to answer one critical question: how much a hotspot predicted from a trained model can be trusted? In this work, we present Litho-GPA, a lithography hotspot detection framework, with Gaussian Process assurance to provide confidence in each prediction. The framework also incorporates a data selection scheme with a sequence of weak classifiers to sample representative data and eventually reduce the amount of training data and lithography simulations needed. Experimental results demonstrate that our Litho-GPA is able to achieve the state-of-the-art accuracy while obtaining on average 28% reduction in false alarms.

Yield learning and optimization are critical for advanced IC design and manufacturing. Recent advance in machine learning has brought a lot of new opportunities in improving the performance and efficiency of IC yield learning and optimization. This paper surveys some recent results of using various machine learning/deep learning techniques for such purpose, including performance modeling under uncertainty, lithography modeling with transfer/active learning, lithography hotspot detection, and IC mask optimization. The state-of-the-art methods are explained, and challenges/opportunities are discussed.

In this paper, we propose a novel methodology for detecting systematic failure patterns at the wafer level for yield learning. Our proposed methodology takes the binary testing results (i.e., pass or fail) of all dies over multiple wafers, cluster these wafers according to their spatial signatures of failures, and eventually identify the underlying systematic failure patterns. Several data processing techniques, including singular value decomposition, hierarchical clustering, etc., are adopted to make the proposed methodology robust to random failures. In addition, a Pseudo-Boolean satisfiability solver is used to extract a minimal set of systematic failure patterns that explain all wafer-level spatial signatures. These patterns help process engineers identify the root causes of failures and accelerate yield learning. The efficacy of our proposed approach is demonstrated by one synthetic data set and one industrial data set.

With the continuous drive toward integrated circuits scaling, efficient performance modeling is becoming more crucial yet more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We exploit the hierarchical structure of a circuit to establish a Bayesian framework where unlabeled data samples are generated to improve modeling accuracy without running additional simulation. Consequently, our proposed method only requires a small number of labeled samples, along with a large number of unlabeled samples obtained at almost no-cost, to accurately learn a performance model. Our numerical experiments demonstrate that the proposed approach achieves up to 3.6× runtime speed-up over the state-of-the-art modeling technique without surrendering any accuracy.

With the continuous drive towards integrated circuits scaling, efficient performance modeling is becoming more crucial yet, more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We exploit the hierarchical structure of a circuit to establish a Bayesian framework where unlabeled data samples are generated to improve modeling accuracy without running additional simulation. Consequently, our proposed method only requires a small number of labeled samples, along with a large number of unlabeled samples obtained at almost no-cost, to accurately learn a performance model. Our numerical experiments demonstrate that the proposed approach achieves up to 3.66x runtime speed-up over the state-of-the-art modeling technique without surrendering any accuracy.

Reconfigurable radio frequency (RF) system has recently emerged as a promising solution to cope with multiple communication standards and high spectrum density. In this paper, we propose a novel optimization framework to efficiently program a reconfigurable RF system. In particular, two novel techniques, including (i) search space reduction by adaptive resolution and (ii) global polynomial optimization based on branch and bound, are developed. When combined with a relaxation iteration scheme, our proposed method offers superior performance when programming a large-scale reconfigurable RF system designed for the WLAN 802.11g standard.

Today's automotive industry is making a bold move to equip vehicles with intelligent driver assistance features. A modern automobile is now equipped with a powerful computing platform to run multiple machine learning algorithms for environment perception (e.g., pedestrian detection) and motion control (e.g., vehicle stabilization). These machine learning systems must be highly robust with extremely small failure rate in order to ensure safe and reliable driving. In this paper, we propose a novel Subset Sampling (SUS) algorithm to efficiently validate a machine learning system. In particular, a Markov Chain Monte Carlo algorithm based on graph mapping is developed to accurately estimate the rare failure rate with a minimal amount of test data, thereby minimizing the validation cost. Our numerical experiments show that SUS achieves 15.2× runtime speed-up over the conventional brute-force Monte Carlo method.

In this paper, we propose a novel methodology for detecting systematic spatial failure patterns at wafer level for yield learning. Our proposed methodology takes the testing results (i.e., pass or fail) of a number of dies over different wafers, cluster all these wafers according to their failures, and eventually identify the underlying spatial failure patterns. Several novel machine learning algorithms, including singular value decomposition, hierarchical clustering, dictionary learning, etc., are developed in order to make the proposed methodology robust to random failures. The efficacy of our proposed approach is demonstrated by an industrial data set.