FinFET technology has become an attractive candidate for high-performance and power-efficient applications. However, its susceptibility to defects increases due to the complexity of the process fabrications and smaller feature sizes. This article proposes compact and low-cost analytical models to evaluate the delay increase in FinFET-based circuits due to resistive open defects. The models rely on electrical simulations to precharacterize the circuit library. Analytical expressions are developed for the three types of resistive opens that may occur in FinFET-based logic cells using multifin and multifinger structures. These types of resistive opens include: a resistive open at the drain or source of the transistors (RODS), a resistive open affecting the gate of a single transistor, and a resistive open affecting the gates of both nMOS and pMOS transistors. Compact analytical models are also developed to evaluate the delay increase due to the resistive open defects under process variations. Independent and correlated process variations are taken into account. The analytical models have been validated against SPICE electrical simulations. The proposed analytical models can be used to evaluate the detectability of resistive open defects, significantly reducing the cost of dealing with different defect sizes. Potential applications of the developed analytical models are delineated. This work allows us to have higher quality and reliable electronic products.

This article proposes an electrical analysis of a new defect mechanism, to be named as b-open defect, which may occur in nanometer technologies due to the use of the Self-Aligned Double Patterning (SADP) technique. In metal lines making use of the SADP technique, a single dust particle may cause the simultaneous occurrence of a bridge defect and an open defect. When the two defects impact the same gates, the electrical effects of the bridge and the open combine and exhibit a new specific electrical behavior; we call this new defect behavior a b-open. As a consequence, existing test generation methodologies may miss defect detection. The electrical behavior of the b-open defect is first analyzed graphically and then validated through extensive SPICE simulations. The test pattern conditions to detect the b-open defect are finally determined, and it is shown that the b-open defect requires specific test generation.

In this paper, we analyze the electrical behavior of a new type of technological defect appearing in the most recent technological process achieving extremely high interconnection density by using the Self-Aligned Double Patterning technique (SADP). This totally new defect mechanism, which could not appear in conventional CMOS technologies, is structurally dependent of the SADP technique and can be considered as a simultaneous combination of Bridge and Open: we consequently named it B-open. The electrical behavior of the B-Open defect is analyzed and shown that the defect exhibits some classical electrical characteristics of Bridge defect and Open defect but also an unprecedented electrical mixed behavior of both defects.

FinFET technology is an attractive candidate for high-performance and power-efficient application and is currently used for several electronic products. FinFET technology incorporates new technologies in the manufacturing processes that may generate new defect topologies which need to be considered during test generation. This paper analyzes the electrical behavior of full open gate defects, i.e., a transistor gate with infinite resistance. It is shown that classical models, called single open (SO) and interconnect open (IO), that have been proposed in the past for CMOS technology are not sufficient in FinFET technology. The modern FinFET-based logic cells using multifin and multifinger design techniques give rise to new specific defect topologies called “subset full open gate defect.” The static and dynamic electrical behaviors of the two new topologies, subset SO (SOsub) and subset IO (IOsub), are analyzed, and the detectability of the defect in the context of Boolean testing and delay testing is derived. The detectability is analyzed taking into account process variation, temperature, and power supply control.

Spin-Transfer-Torque Magnetic RAM (STT-MRAM) is a promising memory technology due to its ultra-integration density capability; nanosecond read and write operation speeds and CMOS/FinFET fabrication process compatibility. As every silicon technology, STT-MRAMs may be affected by fabrication defects, which may be difficult to detect under process variability in deeply scaled transistor technology. This paper proposes a Design-For-Test (DFT) circuit to detect short defects in the STT-MRAM cells. The proposed methodology is based on the observation that a short defect makes different the amplitude of the current entering and leaving the memory cell. The proposed DFT circuitry is robust to process-induced parameters variations in the memory cell. In such way, defects detection probabilities are increased, and a high-quality product can be guaranteed.