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Sepideh Maleki

dblp:180/8237 · DBLP profile ↗
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3ranked-venue papers
3as first author
1since 2021 · last 2021
0000-0002-6508-8061ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author · 1 since 2021Software engineering, systems software and programming languages · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Parallel and multicore computing · 64% Electronic design automation · 19% GPUs and heterogeneous computing · 17%
Theoretical computer science
2 papers
Algorithms and data structures · 41% Coding theory · 41% Computational geometry · 18%

Topics — the 12 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel algorithms › parallel algorithm design
deterministic parallel algorithms
0.512021
BiPart: a parallel and deterministic hypergraph partitioner · PPoPP 2021
Electronic design automation › physical design › circuit partitioning
hypergraph partitioning
0.512021
BiPart: a parallel and deterministic hypergraph partitioner · PPoPP 2021
Parallel and multicore computing › parallel programming models
automatic parallelization
0.312018
Automatic Hierarchical Parallelization of Linear Recurrences · ASPLOS 2018
Parallel and multicore computing › parallel programming models › structured parallelism
hierarchical parallelism
0.312018
Automatic Hierarchical Parallelization of Linear Recurrences · ASPLOS 2018
Coding theory › sequences
linear recurrence sequences
0.312018
Automatic Hierarchical Parallelization of Linear Recurrences · ASPLOS 2018
Algorithms and data structures
parallel algorithms
0.312018
Automatic Hierarchical Parallelization of Linear Recurrences · ASPLOS 2018
GPUs and heterogeneous computing › GPU computing
GPU algorithms
0.212016
Higher-order and tuple-based massively-parallel prefix sums · PLDI 2016
Parallel and multicore computing › parallel algorithms
parallel primitives
0.212016
Higher-order and tuple-based massively-parallel prefix sums · PLDI 2016
Parallel and multicore computing › parallel algorithms › parallel primitives
prefix sum
0.212016
Higher-order and tuple-based massively-parallel prefix sums · PLDI 2016
Computational geometry
partitioning
0.112021
BiPart: a parallel and deterministic hypergraph partitioner · PPoPP 2021
GPUs and heterogeneous computing › GPU programming
CUDA code generation
0.112018
Automatic Hierarchical Parallelization of Linear Recurrences · ASPLOS 2018
GPUs and heterogeneous computing
GPU computing
0.112018
Automatic Hierarchical Parallelization of Linear Recurrences · ASPLOS 2018

Methods — techniques the papers use, named apart from their topics

parallel partitioning · 1.0determinism · 1.0work-efficient parallel algorithm · 0.7domain-specific code generation · 0.7templated kernel · 0.2CUDA · 0.2
YearPublicationVenuePosition
2021 BiPart: a parallel and deterministic hypergraph partitioner
abstract
Hypergraph partitioning is used in many problem domains including VLSI design, linear algebra, Boolean satisfiability, and data mining. Most versions of this problem are NP-complete or NP-hard, so practical hypergraph partitioners generate approximate partitioning solutions for all but the smallest inputs. One way to speed up hypergraph partitioners is to exploit parallelism. However, existing parallel hypergraph partitioners are not deterministic, which is considered unacceptable in domains like VLSI design where the same partitions must be produced every time a given hypergraph is partitioned.
Sepideh Maleki, Udit Agarwal, Martin Burtscher, Keshav Pingali
PPoPP1
2018 Automatic Hierarchical Parallelization of Linear Recurrences
abstract
Linear recurrences encompass many fundamental computations including prefix sums and digital filters. Later result values depend on earlier result values in recurrences, making it a challenge to compute them in parallel. We present a new work- and space-efficient algorithm to compute linear recurrences that is amenable to automatic parallelization and suitable for hierarchical massively-parallel architectures such as GPUs. We implemented our approach in a domain-specific code generator that emits optimized CUDA code. Our evaluation shows that, for standard prefix sums and single-stage IIR filters, the generated code reaches the throughput of memory copy for large inputs, which cannot be surpassed. On higher-order prefix sums, it performs nearly as well as the fastest handwritten code from the literature. On tuple-based prefix sums and digital filters, our automatically parallelized code outperforms the fastest prior implementations.
Sepideh Maleki, Martin Burtscher
ASPLOS1
2016 Higher-order and tuple-based massively-parallel prefix sums
abstract
Prefix sums are an important parallel primitive, especially in massively-parallel programs. This paper discusses two orthogonal generalizations thereof, which we call higher-order and tuple-based prefix sums. Moreover, it describes and evaluates SAM, a GPU-friendly algorithm for computing prefix sums and other scans that directly supports higher orders and tuple values. Its templated CUDA implementation unifies all of these computations in a single 100-statement kernel. SAM is communication-efficient in the sense that it minimizes main-memory accesses. When computing prefix sums of a million or more values, it outperforms Thrust and CUDPP on both a Titan X and a K40 GPU. On the Titan X, SAM reaches memory-copy speeds for large input sizes, which cannot be surpassed. SAM outperforms CUB, the currently fastest conventional prefix sum implementation, by up to a factor of 2.9 on eighth-order prefix sums and by up to a factor of 2.6 on eight-tuple prefix sums.
Sepideh Maleki, Annie Yang, Martin Burtscher
PLDI1