Abstract The popularity of Linux in embedded systems has grown because of its reliability, flexibility, and performance. To ensure these systems meet specific real-time requirements, such as deadlines and throughput, Linux provides support for real-time schedulers and the PREEMPT_RT patch. However, while these tools prioritize high-priority tasks, they can inadvertently compromise the performance of other tasks. Completely Fair Scheduling (CFS) has served as the default scheduling policy in Linux until recently. The CFS is based on the principle that all runnable tasks should share the processor fairly, which helps balance task performance with overall system responsiveness. Despite its benefits, there has been no established method to assess whether real-time requirements are met under CFS. This paper introduces a novel analysis method to estimate the worst-case response time (WCRT) of tasks under CFS, providing a new solution for running real-time tasks in embedded Linux systems. Due to the dynamic nature of CFS, traditional WCRT analysis techniques are not applicable directly. Our technique analyzes how tasks sharing the same processor affect each other, focusing on their vruntime. By examining the bounds of vruntime variation and calculating the maximum interference from other tasks, we effectively estimate the WCRT. We also introduce algorithms that assign the nice values to tasks based on our proposed WCRT analysis technique, ensuring that the real-time requirements are met. We validate the proposed approach through comparative experiments using both a self-developed CFS simulator and an actual Linux system. Our simulator allows for rapid simulations and efficient exploration of various execution scenarios. Through extensive experiments, we empirically validate that our proposed analysis method is efficient with an acceptable level of overestimation. These make it a valuable tool for system verification and design optimization in Linux-based real-time systems.

While task allocation of swarm robots has been extensively researched, resource constraints of robots are rarely considered. In this work, we propose two novel task allocation methods robust to robot failures while considering the resource constraint, limited communication range, and deadline constraint of tasks. The first method, STA (static task allocation) method, finds an optimal task allocation solution at compile-time in terms of the minimum expected finish time, using answer set programming. On the other hand, the DTA (dynamic task allocation) method determines the task candidates for each robot at compile-time considering the resource constraint. It lets each robot select a task autonomously at run-time iteratively by exchanging the task allocation information with its neighbor robots. We assess the efficacy of our methods across three distinct environments: a numerical simulation, a swarm robotics simulation, and real robots. Experimental results show that the proposed methods can effectively tolerate robot failures, and the DTA method is superior to the STA method as the probability of robot failure increases. However, the STA method also exhibits consistent performance and superiority when faced with limitations in inter-robot communication. Additionally, we validate the feasibility of our method in a real-world context by conducting experiments with actual robots.Note to Practitioners—The motivation of this work is to explore how to allocate tasks efficiently to swarm robots to ensure timely completion despite occasional robot failures. In search-and-rescue scenarios, such as in the aftermath of a disaster, the effective use of swarm robots is vital, and the time taken to search is crucial to rescuing individuals within a critical time. Various approaches have been proposed to tackle this problem, taking into account time constraints. However, few studies have considered the impact of hardware constraints on robots. To address this issue, this paper proposes two new strategies to find an optimal allocation: the Static Task Allocation (STA) method and the Dynamic Task Allocation (DTA) method. Our methods are evaluated both on real robots and in simulation environments, demonstrating their suitability for practical application.

This tutorial article addresses a low power computer vision system as an example of a growing application domain of neural networks, exploring various technologies developed to enhance accuracy within the resource and performance constraints imposed by the hardware platform. Focused on a given hardware platform and network model, software optimization techniques, including pruning, quantization, low-rank approximation, and parallelization, aim to satisfy resource and performance constraints while minimizing accuracy loss. Due to the interdependence of model compression approaches, their systematic application is crucial, as evidenced by winning solutions in the Lower Power Image Recognition Challenge (LPIRC) of 2017 and 2018. Recognizing the typical heterogeneity of processing elements in contemporary hardware platforms, the effective utilization through parallelizing neural networks emerges as increasingly vital for performance enhancement. The article advocates for a more impactful strategy—designing a network architecture tailored to a specific hardware platform. For detailed information on each technique, the article provides corresponding references.

In addition to the various requirements that a multi-robot framework should meet, swarm robotics applications also demand robustness, flexibility, and scalability. While several frameworks have been developed for multi-robot operation, they mostly fall short of adequately supporting some of these essential requirements. In this work, we introduce a novel multi-robot programming framework called HiSARM (High-level Specification, Automatic code generation, and Retargetable deployment for Multi-robot systems), designed to assist both mission planners and robot software developers. HiSARM employs a high-level language to enable mission planners to specify collaborative tasks among multiple robots intuitively. From these scripts written in a high-level language, executable robot code is automatically generated. Mission planners can easily customize the executable robot code according to their specific needs within HiSARM. Additionally, HiSARM provides multiple verification environments by introducing a formal intermediate representation and enabling retargetable deployment of the binary file across various domains, including simulation and real robots. For robot software developers, HiSARM eases the development process for robot software developers by categorizing software components and auto-generating swarm-related functions. We tested HiSARM with multiple scenarios in simulation and real robot environments, demonstrating that it effectively supports all the necessary features for multi-robot applications, including swarm operations.

As deep learning inference applications are increasing in embedded devices, an embedded device tends to equip neural processing units (NPUs) in addition to a multi-core CPU and a GPU. NVIDIA Jetson AGX Xavier is an example. For fast and efficient development of deep learning applications, TensorRT is provided as the SDK for high-performance inference, including an optimizer and runtime that delivers low latency and high throughput for deep learning inference applications. Like most deep learning frameworks, TensorRT assumes that the inference is executed on a single processing element, GPU or NPU, not both. In this article, we present a TensorRT-based framework supporting various optimization parameters to accelerate a deep learning application targeted on an NVIDIA Jetson embedded platform with heterogeneous processors, including multi-threading, pipelining, buffer assignment, and network duplication. Since the design space of allocating layers to diverse processing elements and optimizing other parameters is huge, we devise a parameter optimization methodology that consists of a heuristic for balancing pipeline stages among heterogeneous processors and fine-tuning the process for optimizing parameters. With nine real-life benchmarks, we could achieve 101%~680% performance improvement and up to 55% energy reduction over the baseline inference using a GPU only.

Existing software development methodologies mostly assume that an application runs on a single device without concern about the non-functional requirements of an embedded system such as latency and resource consumption. Besides, embedded software is usually developed after the hardware platform is determined, since a non-negligible portion of the code depends on the hardware platform. In this article, we present a novel model-based software synthesis framework for parallel and distributed embedded systems. An application is specified as a set of tasks with the given rules for execution and communication. Having such rules enables us to perform static analysis to check some software errors at compile-time to reduce the verification difficulty. Platform-specific programs are synthesized automatically after the mapping of tasks onto processing elements is determined. The proposed framework is expandable to support new hardware platforms easily. The proposed communication code synthesis method is extensible and flexible to support various communication methods between devices. In addition, the fault-tolerant feature can be added by modifying the task graph automatically according to the selected fault-tolerance configurations by the user. The viability of the proposed software development methodology is evaluated with a real-life surveillance application that runs on six processing elements.

Emulating fault scenarios by injecting faults intentionally is commonly used to test and verify the robustness of a system. As the number of hardware devices integrated into an embedded system tends to increase consistently and the chance of hardware failure is expected to increase in an SoC, it becomes important to emulate fault scenarios caused by hardware-related errors. To this end, we present a kernel-level fault injection framework for ARM-based embedded Linux systems, called FIFA, aiming to investigate the effect of an individual hardware error in a real hardware platform rather than performing statistical analysis by random experiments. FIFA consists of two complementary fault injection techniques, one is based on the Kernel GNU Debugger and the other on hardware breakpoints. Compared with the previous work that emulates bit-flip errors only, FIFA supports other types of errors such as time delay and device failure. The viability of the proposed framework is proved by real-life experiments with an ODROID-XU4 system.