Demo Data from EDBT 2026 / reviewers in the wild / expert
Christian Streitwieser
dblp:180/9941
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
adaptive test |
0.3 | 1 | 2018 | Adaptive Test With Test Escape Estimation for Mixed-Signal ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › hardware verification and test
fault coverage |
0.3 | 1 | 2018 | Adaptive Test With Test Escape Estimation for Mixed-Signal ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › hardware verification and test › analog and mixed-signal test
mixed-signal IC testing |
0.3 | 1 | 2018 | Adaptive Test With Test Escape Estimation for Mixed-Signal ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Methods — techniques the papers use, named apart from their topics
test escape risk estimation · 0.3adaptive test flow · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Adaptive Test With Test Escape Estimation for Mixed-Signal ICsabstractThe standard approach in industry for post-manufacturing testing of mixed-signal circuits is to measure the performances that are included in the data sheet. Despite being accurate and straightforward, this approach involves a high test time since there are numerous performances that need to be measured sequentially by switching the circuit into different test configurations. Adaptive test is a new test paradigm that still adheres to the standard approach, but it adjusts it on-the-fly to the particularities of the circuit under test so as to better control test time and to achieve robust outlier detection. In this paper, we present an adaptive test flow for mixed-signal circuits that has comprehensive user-defined parameters to span the tradeoff between test time savings and fault coverage so as to select an advantageous point on the curve based on test economics. The flow also provides robust test escape risk estimation so as to add confidence to the test process. The proposed idea is demonstrated on a sizable production dataset from a large mixed-signal circuit. Haralampos-G. D. Stratigopoulos, Christian Streitwieser |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2017 | Adaptive test flow for mixed-signal ICsabstractAdaptive test is a promising direction for reducing the manufacturing test cost. It aims to dynamically adjust the test program on a device-by-device or on a wafer-by-wafer basis. Adjusting the test program could involve eliminating tests, changing test limits, re-ordering tests, etc. The objective is to spend the minimum possible test time per device without sacrificing fault coverage. In this paper, we present an adaptive test flow for mixed-signal ICs and we demonstrate its effectiveness on a sizable production dataset from a large mixed-signal IC. The adaptive test flow first eliminates seemingly redundant tests on a wafer-by-wafer basis and then it may refine the test content on a device-by-device basis so as to ensure high fault coverage. In addition, it estimates the test escape risk so as to provide confidence in the binning of devices. Haralampos-G. D. Stratigopoulos, Christian Streitwieser |
VTS | 2 |
| 2016 | Real-time test data acquisition and data processing enabling closed loop control systems for adaptive testabstractBeside it's advantages conventional semiconductor testing is quiet a fixed and rigid process. For instance the list of applied tests, test limits or test flows are always the same for each device. Human involvement is needed for any kind of adaption or improvement. However, in recent times more and more dynamic approaches of testing are getting established in the industry and falling under the category of so-called “adaptive test”. This work demonstrates an adaptive test approach with real-time data acquisition and decision making capabilities. Real-time (RT), implies in this context, data is available and decisions are done after each single measurement within the test sequence of one device under test (DUT). The question of additional overhead in test time and thus feasibility of real-time adaptive test where targeted. With the introduced adaptive test framework, it has been shown that RT adaptive testing with minimal additional test time is feasible. Christian Streitwieser |
ISCAS | 1 |
| 2016 | Real-Time Adaptive Test Algorithm Including Test Escape Estimation Method
Christian Streitwieser |
J. Electron. Test. | 1 |