In this work, a comprehensive analysis and optimization method of electrical and thermal characteristics in 2.5-D integrated circuits (ICs) is performed, including rapid heat distribution modeling, integrated voltage regulator (IVR) chip modeling, and power delivery network (PDN) modeling. Based on the proposed method, chiplet placement, decoupling placement, and IVR parameter settings that compromise the total PDN impedance, IVR impedance, and thermal distribution characteristics can be obtained. First, a rapid thermal analysis method for multiple heat sources is proposed by integrating the equivalent thermal resistance method and commercial tools. The thermal method significantly improves the computational efficiency and reduces the memory usage. Then, we analyze the electrical characteristics of a typical low dropout (LDO) and model the complete 2.5-D PDN, including interposers, chiplets, IVRs, through-silicon vias (TSVs), bumps, decoupling capacitors, and other components. The electrical and thermal problems in the 2.5-D system are formulated and a Metropolis rule-based algorithm is used to derive optimal solutions. Finally, the optimal placement schemes and parameter settings are iterated under different constraints. This method allows for the adjustment of target impedance, noise current, thermal limit, and other constraints based on varying practical situations. In the time-domain analysis, it can be found that the capacitance value is reduced while maintaining the power supply performance. With high accuracy in thermal and electrical modeling, this work provides an in-depth reference for the co-design of chiplet-based 2.5-D ICs.

The utilization of modular chiplets in interposer-based 2.5-D heterogeneous systems simplifies fabrication and design, however, it also introduces significant noise challenges. This paper presents a collaborative jitter-aware optimization in 2.5-D integrated circuits (ICs), incorporating power supply induced jitter (PSIJ), system impedance, target impedance, and decoupling capacitors, based on the hybrid pre-computation and pre-storage/duplicate removal-non-dominated sorting differential evolution (PCPS/DR-NSDE) algorithm. An automatic channel model algorithm and a uniform decoupling capacitor placement strategy are proposed to improve the design efficiency. Then, the system transfer impedance, simultaneous switch current, sensitivity function, and amplification factor are individually modeled, leading to the assembly and verification of the final PSIJ in the 2.5-D system. A PCPS strategy is proposed to handle high-time-consuming modules in the objective function and a DR operation is added to improve algorithm performance. The proposed PCPS/DR-NSDE is faster than traditional algorithms and has optimal hypervolume and coverage-metric (C-metric) indicators. The procedures for further obtaining desired solutions in the Pareto front are discussed. The impact of practical constraints and target impedance is also analyzed. This work provides a collaborative optimization and analysis of jitter, noise, and impedance in 2.5-D systems.

Enhancing the integration of directional couplers is a crucial challenge in the design of wireless communication circuits and systems. This article proposes a design strategy based on through-silicon via (TSV) insertion and neuro-transfer function (Neuro-TF) modeling to achieve miniaturization of coupled-line couplers. By embedding coupled TSV pairs inside the substrate, a planar coupler can be transformed into a 3-D structure with a smaller footprint. Furthermore, a design flow is proposed to achieve the initial parameters of TSV insertion for various application scenarios. Two insertion schemes with regular and coaxial TSVs are applied to handle different requirements and process constraints. The flow also estimates the number of required TSV pairs based on the area reduction target. To reduce dependence on electromagnetic (EM) simulation and make the strategy more widely applicable to various coupler types, Neuro-TF modeling is utilized for optimization after the initial design. Subsequently, the compatibility between the TSV insertion flow and the Neuro-TF method is analyzed to develop a comprehensive miniaturization strategy. The approach has been validated by two design cases through EM simulations. The results indicate that the proposed strategy enables rapid design and achieves area reduction targets effectively.

Interposer and chiplet-based 2.5-D integrated circuit (IC) designs have become a new trend for block-level heterogeneous integration. In this paper, a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5-D IC including interposers, chiplets, through-silicon via (TSV) arrays, bumps, and metal-insulator-metal (MIM) capacitors for simultaneous switch noise (SSN) reduction. Combined with the cascaded PDN assembly method, constraints on routing, delay and proximity distance between the entire system and an impedance-oriented function with multiple critical factors, a hybrid objective function with respect to the 2.5-D PDN is obtained. Integrating the advantages of multiple algorithms, a better hybrid MDP algorithm is designed to optimize the proposed key function. This method adopts the Metropolis rule to avoid the waste of the update mechanism for out-of-boundary particles. The placement, orientation of the chiplets, the on-interposer decoupling capacitor and the constraints of the 2.5-D system are co-optimized to find the optimal solution to eliminate the SSN. The overdesign of the system, different target impedance, different objective-oriented circuit optimization schemes and trade-offs in different constraints are also discussed carefully in this paper for 2.5-D ICs.

An original concept of 3-D through-silicon via (TSV)-based Marchand baluns and its design methodology is proposed for on- chip and 3-D integration. By utilizing a 3-D packaging process that includes a TSV and redistribution layer (RDL), a meander coupling path is established and embedded in the vertical direction of the substrate for balun design. The 3-D structure can effectively reduce the on- chip area while maintaining good balance characteristics. Furthermore, the structure can be flexibly integrated with 3-D integrated circuits (3-D ICs) to realize signal conversion between different stacking tiers. An equivalent circuit model based on the TSV-to-TSV coupling channel and coupled transmission line has been established for initial estimation before electromagnetic (EM) optimization. To shorten the design cycle, a specific flow is proposed to meet the structural particularity and different application scenarios. To verify the design method and flow, a design case is analyzed and EM simulated with the antenna feeding network as the target application. The EM simulation results show that the design can work at 43–82 GHz with an amplitude imbalance of less than 0.3 dB and a phase imbalance of less than 1.3°, which meets the requirements of balanced feeding. It only costs a$0.084\,\,\lambda _{\text {g}}\,{\times }\,0.009\,\,\lambda _{\text {g}}$footprint, which is far lower than that of the conventional planar types.