Laurie Bose

dblp:181/4201 · DBLP profile ↗
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13ranked-venue papers
5as first author
5since 2021 · last 2025
0009-0002-4161-3607ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 11 · 5 first-author · 4 since 2021Graphics, computer vision, multimedia, augmented reality and games · 8 · 4 first-author · 4 since 2021Systems, architecture and hardware · 5 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
7 papers
Hardware accelerators and domain-specific architectures · 75% Emerging computing paradigms · 13% GPUs and heterogeneous computing · 6%
Artificial intelligence
6 papers
Robot navigation and mapping · 47% 3D vision · 33% Efficient and distributed learning · 16%
Computer graphics and multimedia
2 papers
Visualization and visual analytics · 64% Image and video processing · 18% Computational photography and imaging · 18%

Topics — the 16 heaviest of 20, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
in-sensor computing
1.122024
PixelRNN: In-pixel Recurrent Neural Networks for End-to-end-optimized Perception with Neural Sensors · CVPR 2024
A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays · ICCV 2019
Computer vision › 3D vision
feature matching
0.912025
Focal Plane Visual Feature Generation and Matching on a Pixel Processor Array · ICCV 2025
Visualization and visual analytics › flow visualization
feature detection and tracking
0.912025
Descriptor-In-Pixel : Point-Feature Tracking For Pixel Processor Arrays · CVPR 2025
Hardware accelerators and domain-specific architectures
vision accelerator
0.912025
Focal Plane Visual Feature Generation and Matching on a Pixel Processor Array · ICCV 2025
Emerging computing paradigms
neuromorphic computing
0.812024
PixelRNN: In-pixel Recurrent Neural Networks for End-to-end-optimized Perception with Neural Sensors · CVPR 2024
Machine learning › Efficient and distributed learning
model compression
0.412020
Fully Embedding Fast Convolutional Networks on Pixel Processor Arrays · ECCV (29) 2020
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.412019
A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays · ICCV 2019
Robotics › Robot navigation and mapping
visual odometry
0.422017
Visual Odometry for Pixel Processor Arrays · ICCV 2017
Fast depth edge detection and edge based RGB-D SLAM · ICRA 2016
Robotics › Robot navigation and mapping › SLAM › visual SLAM
RGB-D SLAM
0.212016
Fast depth edge detection and edge based RGB-D SLAM · ICRA 2016
Robotics › Robot navigation and mapping › SLAM
visual SLAM
0.212016
Fast depth edge detection and edge based RGB-D SLAM · ICRA 2016
Computational photography and imaging › depth imaging
depth edge detection
0.212016
Fast depth edge detection and edge based RGB-D SLAM · ICRA 2016
Image and video processing
edge detection
0.212016
Fast depth edge detection and edge based RGB-D SLAM · ICRA 2016
Robotics › Robot navigation and mapping › robot mapping
topological mapping
0.112021
Weighted Node Mapping and Localisation on a Pixel Processor Array · ICRA 2021
Robotics › Robot navigation and mapping › place recognition
visual place recognition
0.112021
Weighted Node Mapping and Localisation on a Pixel Processor Array · ICRA 2021
Computer vision › Image recognition and object detection › character recognition
digit recognition
0.112019
A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays · ICCV 2019
Robotics › Robot navigation and mapping
SLAM
0.112016
Fast depth edge detection and edge based RGB-D SLAM · ICRA 2016

Methods — techniques the papers use, named apart from their topics

pixel processor array · 1.7descriptor-in-pixel · 1.7address-event interface · 1.7spatial coherence · 1.0image similarity · 1.0fast convolutional networks · 0.9recurrent neural network · 0.8convolutional neural network · 0.8binary operations · 0.8ternary weight quantization · 0.4max-pooling · 0.4max pooling · 0.4image scaling · 0.3image rotation · 0.3image alignment · 0.3back-projection · 0.2ICP registration · 0.2
YearPublicationVenuePosition
2025 Descriptor-In-Pixel : Point-Feature Tracking For Pixel Processor Arrays
abstract
This paper presents a novel approach for joint point-feature detection and tracking, designed specifically for Pixel Processor Array (PPA) vision sensors. Instead of standard pixels, PPA sensors consist of thousands of "pixel-processors", enabling massive parallel computation of visual data at the point of light capture. Our approach performs all computation entirely in-pixel, meaning no raw image data need ever leave the sensor for external processing. We introduce a Descriptor-In-Pixel paradigm, in which a feature descriptor is held within the memory of each pixel-processor. The PPA’s architecture enables the response of every processor’s descriptor, upon the current image, to be computed in parallel. This produces a"descriptor response map" which, by generating the correct layout of descriptors across the pixel-processors, can be used for both point-feature detection and tracking. This reduces sensor output to just sparse feature locations and descriptors, read-out via an address-event interface, giving a greater than 1000× reduction in data transfer compared to raw image output. The sparse readout and complete utilization of all pixel-processors makes our approach very efficient. Our implementation upon the SCAMP-7 PPA prototype runs at over 3000 FPS (Frames Per Second), tracking point-features reliably under violent motion. This is the first work performing point-feature detection and tracking entirely in-pixel.1
Laurie Bose, Jianing Chen 0005, Piotr Dudek
CVPR1
2025 Focal Plane Visual Feature Generation and Matching on a Pixel Processor Array
Laurie Bose, Jianing Chen 0005, Piotr Dudek, Walterio W. Mayol-Cuevas
ICCV2
2024 PixelRNN: In-pixel Recurrent Neural Networks for End-to-end-optimized Perception with Neural Sensors
abstract
Conventional image sensors digitize high-resolution images at fast frame rates, producing a large amount of data that needs to be transmitted off the sensor for fur-ther processing. This is challenging for perception system operating on edge devices, because communication is power inefficient and induces latency. Fueled by innovations in stacked image sensor fabrication, emerging sensor-processors offer programmability and processing capabilities directly on the sensor. We exploit these capabilities by developing an efficient recurrent neural network architecture, PixelRNN, that encodes spatio-temporal features on the sensor using purely binary operations. PixelRNN reduces the amount of data to be transmitted off the sensor by factors up to 256 compared to the raw sensor data while offering competitive accuracy for hand gesture recognition and lip reading tasks. We experimentally validate PixelRNN using a prototype implementation on the SCAMP-5 sensor-processor platform.
Haley M. So, Laurie Bose, Piotr Dudek, Gordon Wetzstein
CVPR2
2021 Weighted Node Mapping and Localisation on a Pixel Processor Array
abstract
This paper implements and demonstrates visual route mapping and localisation upon a Pixel Processor Array (PPA). The PPA sensor comprises of an array of Processing Elements (PEs), each of which can capture and process visual information directly. This provides significant parallel processing power allowing novel ways in which information can be processed on-sensor. Our method predicts the correct node within a topological map generated from an image sequence by measuring image similarities, spatial coherence, and exploiting the parallel nature of the PPA. Our implementation runs at +300Hz on large public datasets with +2K locations requiring 2.5W at 500 GOPS/W. We compare vs traditionally implemented methods demonstrating better F-1 performance even on simulation. As far as we are aware, we present the first on-sensor mapping and localisation system running entirely on-sensor.
Hector Castillo-Elizalde, Laurie Bose, Walterio W. Mayol-Cuevas
ICRA3
2021 Agile reactive navigation for a non-holonomic mobile robot using a pixel processor array
abstract
Abstract This paper presents an agile reactive navigation strategy for driving a non‐holonomic ground vehicle around a pre‐set course of gates in a cluttered environment using a low‐cost processor array sensor. This enables machine vision tasks to be performed directly upon the sensor's image plane, rather than using a separate general‐purpose computer. The authors demonstrate a small ground vehicle running through or avoiding multiple gates at high speed using minimal computational resources. To achieve this, target tracking algorithms are developed for the Pixel Processing Array and captured images are then processed directly on the vision sensor acquiring target information for controlling the ground vehicle. The algorithm can run at up to 2000 fps outdoors and 200 fps at indoor illumination levels. Conducting image processing at the sensor level avoids the bottleneck of image transfer encountered in conventional sensors. The real‐time performance of on‐board image processing and robustness is validated through experiments. Experimental results demonstrate the algorithm's ability to enable a ground vehicle to navigate at an average speed of 2.20 m/s for passing through multiple gates and 3.88 m/s for a ‘slalom’ task in an environment featuring significant visual clutter.
Laurie Bose, Colin Greatwood, Jianing Chen 0005, Rui Fan 0001, Tom Richardson 0002, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
IET Image Process.2
2020 High-speed Light-weight CNN Inference via Strided Convolutions on a Pixel Processor Array
Laurie Bose, Jianing Chen 0005, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
BMVC2
2020 Fully Embedding Fast Convolutional Networks on Pixel Processor Arrays
Laurie Bose, Piotr Dudek, Jianing Chen 0005, Stephen J. Carey, Walterio W. Mayol-Cuevas
ECCV (29)1
2020 Live Demonstration: CNN Inference on the Focal Plane with a Pixel Processor Array
abstract
We present a novel method of CNN inference on a pixel processor array device, demonstrating it using a handwritten digit (digits 0-9) classification task, with all steps of the neural network computation performed on the focal plane. The vision chip that we deploy (SCAMP-7) has a 256×256 array of processor elements (PE) integrated within the image sensor. The algorithm runs at over 3000 frames per second (FPS) and over 90% classification accuracy, with the sensor chip only outputting ten scalar values corresponding to the classification scores.
Stephen J. Carey, Laurie Bose, Tom Richardson 0002, Walterio W. Mayol-Cuevas, Jianing Chen 0005, Piotr Dudek
ISCAS2
2019 A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays
abstract
We present a convolutional neural network implementation for pixel processor array (PPA) sensors. PPA hardware consists of a fine-grained array of general-purpose processing elements, each capable of light capture, data storage, program execution, and communication with neighboring elements. This allows images to be stored and manipulated directly at the point of light capture, rather than having to transfer images to external processing hardware. Our CNN approach divides this array up into 4x4 blocks of processing elements, essentially trading-off image resolution for increased local memory capacity per 4x4 ”pixel”. We implement parallel operations for image addition, subtraction and bit-shifting images in this 4x4 block format. Using these components we formulate how to perform ternary weight convolutions upon these images, compactly store results of such convolutions, perform max-pooling, and transfer the resulting sub-sampled data to an attached micro-controller. We train ternary weight filter CNNs for digit recognition and a simple tracking task, and demonstrate inference of these networks upon the SCAMP5 PPA system. This work represents a first step towards embedding neural network processing capability directly onto the focal plane of a sensor.
Laurie Bose, Piotr Dudek, Jianing Chen 0005, Stephen J. Carey, Walterio W. Mayol-Cuevas
ICCV1
2018 Perspective Correcting Visual Odometry for Agile MAVs using a Pixel Processor Array
abstract
This paper presents a visual odometry approach using a Pixel Processor Array (PPA) camera, specifically, the SCAMP-5 vision chip. In this device, each pixel is capable of storing data and performing computation, enabling a variety of computer vision tasks to be carried out directly upon the sensor itself. In this work the PPA performs HDR edge detection, perspective correction and image alignment based odometry, allowing the position and heading of a MAV to be tracked at several hundred frames per second. We evaluate our PPA based approach by direct comparison with a motion capture system for a variety of trajectories. These include rapid accelerations that would incur significant motion blur at low frame rates, and lighting conditions that would typically lead to under or over exposure of image detail. Such challenging conditions would often lead to unusable images when relying on traditional image sensors.
Colin Greatwood, Laurie Bose, Tom Richardson 0002, Walterio W. Mayol-Cuevas, Jianing Chen 0005, Stephen J. Carey, Piotr Dudek
IROS2
2017 Visual Odometry for Pixel Processor Arrays
abstract
We present an approach of estimating constrained egomotion on a Pixel Processor Array (PPA). These devices embed processing and data storage capability into the pixels of the image sensor, allowing for fast and low power parallel computation directly on the image-plane. Rather than the standard visual pipeline whereby whole images are transferred to an external general processing unit, our approach performs all computation upon the PPA itself, with the camera's estimated motion as the only information output. Our approach estimates 3D rotation and a 1D scale-less estimate of translation. We introduce methods of image scaling, rotation and alignment which are performed solely upon the PPA itself and form the basis for conducting motion estimation. We demonstrate the algorithms on a SCAMP-5 vision chip, achieving frame rates >1000Hz at ~2W power consumption.
Laurie Bose, Jianing Chen 0005, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
ICCV1
2017 Tracking control of a UAV with a parallel visual processor
abstract
This paper presents a vision-based control strategy for tracking a ground target using a novel vision sensor featuring a processor for each pixel element. This enables computer vision tasks to be carried out directly on the focal plane in a highly efficient manner rather than using a separate general purpose computer. The strategy enables a small, agile quadrotor Unmanned Air Vehicle (UAV) to track the target from close range using minimal computational effort and with low power consumption. To evaluate the system we target a vehicle driven by chaotic dual-pendulum trajectories. Target proximity and the large, unpredictable accelerations of the vehicle cause challenges for the UAV in keeping it within the downward facing camera's field of view (FoV). A state observer is used to smooth out predictions of the target's location and, importantly, estimate velocity. Experimental results also demonstrate that it is possible to continue to re-acquire and follow the target during short periods of loss in target visibility. The tracking algorithm exploits the parallel nature of the visual sensor, enabling high rate image processing ahead of any communication bottleneck with the UAV controller. With the vision chip carrying out the most intense visual information processing, it is computationally trivial to compute all of the controls for tracking onboard. This work is directed toward visual agile robots that are power efficient and that ferry only useful data around the information and control pathways.
Colin Greatwood, Laurie Bose, Tom Richardson 0002, Walterio W. Mayol-Cuevas, Jianing Chen 0005, Stephen J. Carey, Piotr Dudek
IROS2
2016 Fast depth edge detection and edge based RGB-D SLAM
abstract
This paper presents a method of occluding depth edge-detection targeted towards RGB-D video streams and explores the use of these and other edge features in RGB-D SLAM. The proposed depth edge-detection approach uses prior information obtained from the previous RGB-D video frame to determine which areas of the current depth image are likely to contain edges due to image similarity. By limiting the search for edges to these areas a significant amount of computation time is saved compared to searching the entire image. Pixels belonging to both the depth and colour edges of an RGB-D image can be back projected using the depth component to form 3D point clouds of edge points. Registration between such edge point clouds is achieved using ICP and we present a realtime RGB-D SLAM system utilizing such back projected edge features. Experimental results are presented demonstrating the performance of both the proposed depth edge-detection and SLAM system using publicly available datasets.
Laurie Bose, Arthur G. Richards
ICRA1