EDBT 2026 Demo / reviewers in the wild / expert
P. A. Lord
dblp:181/5119
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1963
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Storage systems · 50% Memory systems · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
memory architecture |
0.0 | 1 | 1963 | A Delay-Line Push-Down List · IEEE Trans. Electron. Comput. 1963 |
Storage systems
storage devices |
0.0 | 1 | 1963 | A Delay-Line Push-Down List · IEEE Trans. Electron. Comput. 1963 |
Methods — techniques the papers use, named apart from their topics
delay line storage · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1963 | A Delay-Line Push-Down Listabstract``List structure'' arrangements of information are increasingly being used in digital data-processing applications. A ``push-down'' list is one manipulated in a last-in, first-out manner. The implementation of such a list structure is possible in a variety of ways. This paper describes one such method which uses a delay line as a storage device. P. A. Lord, Cyril J. Tunis, H. L. Witter |
IEEE Trans. Electron. Comput. | 1 |