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Michael J. Lanigan

dblp:181/6333 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1962
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › cache management
cache replacement
0.011962
One-Level Storage System · IRE Trans. Electron. Comput. 1962
Memory systems › memory management
single level store
0.011962
One-Level Storage System · IRE Trans. Electron. Comput. 1962
Memory systems › memory management
virtual memory
0.011962
One-Level Storage System · IRE Trans. Electron. Comput. 1962

Methods — techniques the papers use, named apart from their topics

automatic storage hierarchy management · 0.0
YearPublicationVenuePosition
1962 One-Level Storage System
abstract
After a brief survey of the basic Atlas machine, the paper describes an automatic system which in principle can be applied to any combination of two storage systems so that the combination can be regarded by the machine user as a single level. The actual system described relates to a fast core store-drum combination. The effect of the system on instruction times is illustrated, and the tape transfer system is also introduced since it fits basically in through the same hardware. The scheme incorporates a ``learning'' program, a technique which can be of greater importance in future computers.
Tom Kilburn, David B. G. Edwards, Michael J. Lanigan, Frank H. Sumner
IRE Trans. Electron. Comput.3