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N. Parezanovic

dblp:181/6342 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1962
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 87% Electronic design automation · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.011962
Accuracy Improvements of the Tapped-Potentiometer Function Generators · IRE Trans. Electron. Comput. 1962
Integrated circuit design › analog and mixed-signal circuits
function generator
0.011962
Accuracy Improvements of the Tapped-Potentiometer Function Generators · IRE Trans. Electron. Comput. 1962
Electronic design automation
circuit analysis
0.011962
Accuracy Improvements of the Tapped-Potentiometer Function Generators · IRE Trans. Electron. Comput. 1962
YearPublicationVenuePosition
1962 Accuracy Improvements of the Tapped-Potentiometer Function Generators
abstract
This paper describes a procedure for correct calculation of the resistance of the potentiometer function generator, including the load resistance of the generator. The possibility of generating the function by taking inequidistant values of the independent variable is also described as is the possibility of generating some special functions.
N. Parezanovic, M. Dujmovic
IRE Trans. Electron. Comput.1