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Benjamin Rabinovici

dblp:181/6358 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1962
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.021962
Tunnel-Diode Full Binary Adder · IRE Trans. Electron. Comput. 1962
A Transistor Flip-Flop Full Binary Adder · IRE Trans. Electron. Comput. 1962
Integrated circuit design › digital circuit design › arithmetic circuit design
binary adder
0.011962
Tunnel-Diode Full Binary Adder · IRE Trans. Electron. Comput. 1962
Integrated circuit design › digital circuit design › sequential circuit design
flip-flop
0.011962
A Transistor Flip-Flop Full Binary Adder · IRE Trans. Electron. Comput. 1962
Integrated circuit design › digital circuit design › arithmetic circuit design
full adder
0.011962
A Transistor Flip-Flop Full Binary Adder · IRE Trans. Electron. Comput. 1962
Integrated circuit design › digital circuit design
logic design
0.011962
Tunnel-Diode Full Binary Adder · IRE Trans. Electron. Comput. 1962
Integrated circuit design
low-power circuit design
0.011962
Tunnel-Diode Full Binary Adder · IRE Trans. Electron. Comput. 1962

Methods — techniques the papers use, named apart from their topics

circuit analysis · 0.0analytical modeling · 0.0
YearPublicationVenuePosition
1962 A Transistor Flip-Flop Full Binary Adder
Benjamin Rabinovici, Charles A. Renton
IRE Trans. Electron. Comput.1
1962 Tunnel-Diode Full Binary Adder
abstract
A full binary adder utilizing a single tunnel diode and three resistors as its basic components is described, the circuit design criteria is outlined and values for a typical case are computed. The operating rate of the adder was determined analytically to be approximately 3 nsec. Experimental results obtained with a practical circuit that employed a 1N2939 tunnel diode were in good agreement with the analytical findings. The Sum and Carry outputs were 130 mv and 300 mv, respectively. These outputs need to be amplified if used to drive identical stages since there is no gain in this circuit. Since a full binary adder is a multipurpose logic element, a simple, compact, full binary adder that contains few components presents attractive possibilities for new computer logical schemes. This adder offers circuit simplicity and stability and is particularly suitable for application where low-power dissipation and compactness are desired.
Charles A. Renton, Benjamin Rabinovici
IRE Trans. Electron. Comput.2