Yinhao Zhou

dblp:181/7431 · DBLP profile ↗
← Back
4ranked-venue papers
0as first author
4since 2021 · last 2026
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021
YearPublicationVenuePosition
2026 RTL Verification for Secure Speculation Using Cascaded Two-Phase Information Flow Tracking
Yinhao Zhou, Zhenfeng Li, Yanyun Lu
ASP-DAC3
2025 B-HTRecognizer: Bitwise Hardware Trojan Localization Using Graph Attention Networks
abstract
Hardware Trojans (HTs), which are malicious modifications injected into an integrated circuit (IC) by untrusted vendors, pose a significant threat to circuit design due to their highly destructive nature. The covert characteristics of HTs present challenges for detection methods, such as the requirement for transferable unknown circuit detection, the extensive manual effort involved, and the difficulty in fine-grained localization. To address these issues, we present B-HTRecognizer, a novel learning-based classification methodology that leverages HT similarities to automatically localize HTs in unknown designs at the bit level. In this study, we convert Verilog hardware description language (HDL) design into bit-level edge-featured data flow graphs (DFGs) using graph attention network (GAT) for multidimensional feature extraction of HTs. The bit-level feature extraction can achieve better performance when dealing with Trigger-hidden HTs, which are highly likely to bypass existing GNN solutions. Furthermore, we construct an open-source HT dataset named TrustHub IMEex The HTs dataset is publicly available athttps://www.scidb.cn/en/anonymous/QjNFdmUywhich extends the TrustHub dataset to facilitate effective training and precise localization. Through rigorous experimentation across different designs, our proposed method achieves 84% precision and 93% recall in noncross-design settings, and a recall rate of 77% on a 32-bit RISC-V design in cross-design testing.
Zhenyu Fan, Yinhao Zhou, Ying Li 0056
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2024 Application of SNNS Model Based On Multi-Dimensional Attention In Drone Radio Frequency Signal Classification
abstract
Spiking Neural Networks (SNNs) are attracting attention due to their energy efficiency and importance in neuromorphic computing. Therefore, we propose an SNN-based method for classifying drone RF signals in complex electromagnetic environments. Specifically, we designed a new SNNs model called Spiking-EfficientNet based on EfficientNetV2 and improved its performance with a multidimensional attention mechanism. Experimental results demonstrate that Spiking-EfficientNet achieved classification accuracy of 99.13% and 96.02% on the ZK RF and DroneDetectV2 datasets. Importantly, Spiking-EfficientNet not only outperforms traditional Artificial Neural Networks (ANNs) in performance, but also exhibits significantly lower energy consumption. The energy consumption is only 20.1% of EfficientNetV2, 2.56% of VGG11, 10.71% of ResNet18, and 61.15% of MobileNetV2. This study demonstrates the significant potential of SNNs in drone RF signal classification and provides a low-power solution.
Zheng Si, Jianyu Liu, Yinhao Zhou
ICASSP4
2023 A Portable Hardware Trojan Detection Using Graph Attention Networks
abstract
Among all hardware security threats, the malicious circuits surreptitiously inserted into third-Party Intellectual Property (3PIP) cores, known as Hardware Trojans (HTs), is one of the main concerns. The early discovery of HTs is crucial because any countermeasure after the fabrication process would be expensive or unavailable. Graph Neural Networks (GNN), with the intuitive graph representation of a hardware design, has emerged as a powerful technique to solve this problem. However, most of these networks have two limitations, including the loss of dynamic structural features and the portability issue of using trained models in other designs. To this end, we address such limitations by proposing a new edge-featured Data Flow Graph (DFG) generation method that combines circuit structures with simulation data to establish HTs detection based on Graph Attention Networks (GAT). The solution is utilizing GAT to extract the HTs features from DFG, then identifying the known and unknown HTs hidden in different circuits. We evaluate this methodology on our dataset by expanding Trusthub HTs benchmarks. The results show that our approach can realize the HTs detection with high recall and precision in a short time. Compared with the previous method, our method has more scalable capability and excellent prospects in HTs detection.
Yinhao Zhou, Ying Li 0056
ATS2