The 2-D median filter, one of the oldest and most well-established image-filtering techniques, still sees widespread use throughout computer vision. Despite its relative algorithmic simplicity, accelerating the 2-D median filter via a hardware implementation becomes increasingly challenging as the window size increases, since the resources required grow quartically with the window size. Previous works, in a non-FPGA context, have shown that separately applying several directional median filters to an image, and then taking the median of their results, yields performance that is competitive with, and in some cases even better than, that of a classic 2-D window median. Inspired by these approaches, we propose a novel way of substituting a 2-D median filter on an FPGA with a sequence of directional median filters, in our case arranged as a pipeline, in the pursuit of an FPGA implementation that achieves better scalability and hardware efficiency without sacrificing accuracy. We empirically show that the combination of three particular directional filters, in any order, achieves this, whilst requiring quadratically fewer resources on the FPGA and allowing for much higher throughput.

The 2-D median filter, one of the oldest and most well-established image-filtering techniques, still sees widespread use throughout computer vision. Despite its relative algorithmic simplicity, accelerating the 2-D median filter via a hardware implementation becomes increasingly challenging as the window size increases, since the resources required grow quadratically with the window size. Previous works, in a non-FPGA context, have shown that applying a sequence of multiple directional median filters to an image yields results that are competitive with, and in some cases even better than, those of a classic 2-D window median. Inspired by these approaches, we propose a novel way of substituting a 2-D median filter on an FPGA with a sequence of directional median filters, in our case in the pursuit of an FPGA implementation that achieves better scalability and hardware efficiency without sacrificing accuracy. We empirically show that the combination of three particular directional filters, in any order, achieves this, whilst requiring quadratically fewer resources on the FPGA. Our approach allows for much higher throughput and is easier to implement as a pipeline.

Real world applications of stereo depth estimation require models that are robust to dynamic variations in the environment. Even though deep learning based stereo methods are successful, they often fail to generalize to unseen variations in the environment, making them less suitable for practical applications such as autonomous driving. In this work, we introduce a ``learning-to-adapt'' framework that enables deep stereo methods to continuously adapt to new target domains in an unsupervised manner. Specifically, our approach incorporates the adaptation procedure into the learning objective to obtain a base set of parameters that are better suited for unsupervised online adaptation. To further improve the quality of the adaptation, we learn a confidence measure that effectively masks the errors introduced during the unsupervised adaptation. We evaluate our method on synthetic and real-world stereo datasets and our experiments evidence that learning-to-adapt is, indeed beneficial for online adaptation on vastly different domains.

Stereo depth estimation is used for many computer vision applications. Though many popular methods strive solely for depth quality, for real-time mobile applications (e.g. prosthetic glasses or micro-UAVs), speed and power efficiency are equally, if not more, important. Many real-world systems rely on Semi-Global Matching (SGM) to achieve a good accuracy vs. speed balance, but power efficiency is hard to achieve with conventional hardware, making the use of embedded devices such as FPGAs attractive for low-power applications. However, the full SGM algorithm is ill-suited to deployment on FPGAs, and so most FPGA variants of it are partial, at the expense of accuracy. In a non-FPGA context, the accuracy of SGM has been improved by More Global Matching (MGM), which also helps tackle the streaking artifacts that afflict SGM. In this paper, we propose a novel, resource-efficient method that is inspired by MGM's techniques for improving depth quality, but which can be implemented to run in real time on a low-power FPGA. Through evaluation on multiple datasets (KITTI and Middlebury), we show that in comparison to other real-time capable stereo approaches, we can achieve a state-of-the-art balance between accuracy, power efficiency and speed, making our approach highly desirable for use in real-time systems with limited power.