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Demo Data from EDBT 2026 / reviewers in the wild / expert

James Bruce Wilson

dblp:182/0124 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1976
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 75% Integrated circuit design · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › arithmetic unit
arithmetic unit design		 0.011961
An Algorithm for Rapid Binary Division · IRE Trans. Electron. Comput. 1961
Processor architecture and microarchitecture › division algorithm
binary division		 0.011961
An Algorithm for Rapid Binary Division · IRE Trans. Electron. Comput. 1961
Integrated circuit design
digital arithmetic circuits		 0.011961
An Algorithm for Rapid Binary Division · IRE Trans. Electron. Comput. 1961
Processor architecture and microarchitecture
division algorithm		 0.011961
An Algorithm for Rapid Binary Division · IRE Trans. Electron. Comput. 1961

Methods — techniques the papers use, named apart from their topics

leading-bit examination · 0.0
YearPublicationVenuePosition
1976 The Precise Handling of Qualitative Relationships
Robert S. Ledley, James Bruce Wilson
 Comput. Lang.2
1961 An Algorithm for Rapid Binary Division
abstract
A new algorithm is given for reducing the number of additions and subtractions required in binary division in a computer. The algorithm is presented in two parts. A simplified algorithm, which can significantly reduce the number of operations with minimal additional circuitry, is used to develop the justification of the method. The complete algorithm introduces modifications which allow the minimum number of operations by examination of no more than the leading five bits of the divisor and remainder. An average of two-thirds can be saved in the number of operations.
James Bruce Wilson, Robert S. Ledley
 IRE Trans. Electron. Comput.1