Resistive sensors are used extensively to sense various target parameters in industrial applications. However, the environment near the target parameter is incompatible with the electronics necessary for conditioning signals from the resistive sensor. The resistive sensor is placed very close to the target parameter to maintain high transduction reliability. Consequently, the sensor is connected using long wires to the primary signal conditioning circuit. The resistance of these lead wires acts across the sensor resistance and reduces the transduction accuracy. In this work, a bipolar current excited lead resistance compensated 3-wire resistance measurement system is proposed. The proposed measurement system compensates for component and lead wire mismatches, allowing sensor quantification even when lead wires have different values. The system also compensates for the sensor baseline resistance, enhancing the resolution and the voltage headroom. The system demonstrates a resolution of 1 mΩ with an SNR of more than 75 dB with a worst-case error of less than 1%. The lead wire resistance compensation range is experimentally verified from 1 to 100 Ω.

A cryogenic complementary metal-oxide semiconductor (cryo-CMOS) ultra-high-frequency (UHF) analog filter designed for enabling scalable quantum control interfaces is presented in this work. Effective filtering at both analog-to-digital and digital-to-analog conversion stages is critical to maintain signal integrity and achieve high-fidelity qubit control and readout. The proposed filter employs a differential flipped-voltage-follower-based topology, facilitating compact single-branch design, high linearity, and low power consumption. An on-chip buffer stage and a de-embedding technique for precise chip measurements are also presented. The filter is designed using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FD-SOI) technology, leveraging a low-voltage operation of 0.8 V, facilitating low power consumption. A key advantage of using FD-SOI technology for enabling cryogenic quantum computing hardware is the additional degree of freedom provided by the available back-gate transistor connection through which the – increased by the cryogenic (4 K) environment – threshold voltage can be restored. The filter's performance is validated through post-layout simulations, demonstrating improved performance compared to the state-of-the-art literature regarding bandwidth, linearity, and power consumption.

This brief presents a new method to characterize the linearity of on-chip filters with accurate characterization of the filter’s transfer function (TF) in both its bandpass and stopband. Unlike conventional methods, this approach uses only one buffer, simplifying the design and improving accuracy. The filter and buffer are designed using GlobalFoundries (GF) 22-nm FDX technology, incorporating a back-gate biasing tuning mechanism in the buffer design that aims to maintain the performance of the buffer under process variation. The postlayout simulations demonstrate that the new method achieves a filter linearity of$\text {IIP3}=10.46~\text {dBm}$, with an accuracy of 99.4% compared to the standalone filter’s linearity. Similar consistency is observed across process corners.

A systematic research on the development of cryogenic complementary metal-oxide semiconductor (cryo-CMOS) circuits, for implementing the required control electronics to manipulate the quantum bit (qubit) state, is performed over the last few years. Scalability constitutes a key term regarding the evolution of quantum computing from theory to practical application and CMOS technology has been proven to be a promising candidate for implementing the coveted scalable next-generation quantum computers (QCs). Mixed-signal blocks, used for uniting the analog and digital domains, play a key role in the efficient functionality of the qubit control/readout system, thus there is an ever-increasing interest in their high-performance circuit realization. The critical challenge in this venture is to achieve efficient cryogenic operation at low temperatures, i.e., close to the qubit around 4 K, simultaneously keeping power requirements at low values. An overview and comparison of the cryo-CMOS Digital-to-Analog converter (DAC) and Analog-to-Digital converter (ADC) circuit implementations for quantum computing applications that heretofore have been proposed in the literature is presented in this work. A discussion on the challenges and future strategic steps that are henceforth required to proceed toward the development of a functional scalable quantum computer is also conducted.

This paper presents a low-power integrated wireless telemetry system (Bio-WiTel) for healthcare applications in 401-406 MHz frequency band of medical device radiocommunication (MedRadio) spectrum. In this paper, necessary design considerations for telemetry system for short-range (upto 3 m) communication of biosignals are presented. These considerations help greatly in making important design decisions, which eventually lead to a simple, low power, robust, and reliable wireless system implementation. Transmitter (TX) and receiver (RX) of Bio-WiTel system have been fabricated in 180 nm mixed mode CMOS technology. While radiating -18 dBm output power to a 50 antenna, the packaged TX IC consumes 250 μW power in 100% on state from 1 V supply, whereas the RX IC consumes 990 μW power from 1.8 V supply with a sensitivity of -75 dBm. Measurement results show that TX fulfils the spectral mask requirement at a maximum data rate of 72 kb/s. The measured bit error rate (BER) of RX is less than for a data rate of 200 kb/s. The proposed Bio-WiTel system is tested successfully in home and hospital environments for the communication of electrocardiogram and photoplethysmogram signals at a data rate of 57.6 kb/s with a measured BER of <10 for a maximum distance of 3 m.