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Edwin Peguero

dblp:182/9321 · DBLP profile ↗
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2ranked-venue papers
1as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 first-authorSystems, architecture and hardware · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 67% Processor architecture and microarchitecture · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
many-core architecture
0.512021
Software-Defined Vector Processing on Manycore Fabrics · MICRO 2021
Parallel and multicore computing
parallel programming models and runtimes
0.512021
Software-Defined Vector Processing on Manycore Fabrics · MICRO 2021
Parallel and multicore computing › parallel architecture
SIMD/MIMD execution
0.512021
Software-Defined Vector Processing on Manycore Fabrics · MICRO 2021

Methods — techniques the papers use, named apart from their topics

decoupled access/execute · 0.5
YearPublicationVenuePosition
2021 Software-Defined Vector Processing on Manycore Fabrics
abstract
We describe a tiled architecture that can fluidly transition between manycore (MIMD) and vector (SIMD) execution. The hardware provides a software-defined vector programming model that lets applications aggregate groups of manycore tiles into logical vector engines. In manycore mode, the machine behaves as a standard parallel processor. In vector mode, groups of tiles repurpose their functional units as vector execution lanes and scratchpads as vector memory banks. The key mechanism is an instruction forwarding network: a single tile fetches instructions and sends them to other trailing cores. Most cores disable their frontends and instruction caches, so vector groups amortize the intrinsic hardware costs of von Neumann control. Vector groups also use a decoupled access/execute scheme to centralize their memory requests and issue coalesced, wide loads.
Philip Bedoukian, Neil Adit, Edwin Peguero, Adrian Sampson
MICRO3
2016 Assessing Jitter in Sensor Time Series from Android Mobile Devices
abstract
This paper is motivated by work on a real-time Android navigation system using accelerometer, gyroscope, and camera data. We observed that our attempts at combining data from these different sensors yielded time series with jitter, i.e., inaccurate timestamps, that negatively affected program correctness and reliability. Thus, the aim of this paper is to help Android developers anticipate, assess, and understand problems with data quality in sensor-dependent applications. Our analysis focuses on jitter in timestamps obtained from Android's SensorManager and CameraManager services. We demonstrate the presence and severity of jitter obtained through these services and explain the characteristics of Android that originate jitter, resulting in a taxonomy of the various sources of jitter. Finally, we discuss the results of a quantitative analysis of jitter performed on three Android mobile devices (HTC One M8, Google Nexus 5, and Asus Zenfone 2) and provide recommendations on how Android developers can design sensing applications that will behave correctly across the majority of mobile devices.
Edwin Peguero, Miguel A. Labrador, Brittany Cook
SMARTCOMP1