Demo Data from EDBT 2026 / reviewers in the wild / expert
David A. Aaronson
dblp:182/9812
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1960
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 87% Integrated circuit design · 13% | |
| Computer networks
1 paper |
Physical-layer communications · 100% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
delay-line memory |
0.0 | 1 | 1960 | Magnetostrictive Ultrasonic Delay Lines for a PCM Communication System · IRE Trans. Electron. Comput. 1960 |
Memory systems › delay-line memory
magnetostrictive delay lines |
0.0 | 1 | 1960 | Magnetostrictive Ultrasonic Delay Lines for a PCM Communication System · IRE Trans. Electron. Comput. 1960 |
Integrated circuit design › memory circuit design
memory elements |
0.0 | 1 | 1960 | Magnetostrictive Ultrasonic Delay Lines for a PCM Communication System · IRE Trans. Electron. Comput. 1960 |
Methods — techniques the papers use, named apart from their topics
temperature compensation · 0.0magnetostrictive delay lines · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1960 | Magnetostrictive Ultrasonic Delay Lines for a PCM Communication SystemabstractA servo-operated delay-line pad and a temperature-compensated delay-line memory, both magnetostrictively driven at 1.5 mc, have been used in an experimental PCM communication system.1 The delay-line pad automatically compensates for external delay changes as small as plus or minus 8 mμsec at a rate of 75 mμsec second. The delay-line memory stores 192 bits which are available serially with an access time of 125 μsec. Both applications use the same basic delay lines which consist of a length of 0.003-inch diameter supermendur wire, two tiny solenoids, and a supporting structure. David A. Aaronson, Dennis B. James |
IRE Trans. Electron. Comput. | 1 |