Ferroelectric random access memory (FeRAM) is a promising candidate to further dynamic random access memory (DRAM) scaling. However, the design of the FeRAM bit cell is nontrivial as the ferroelectric device model is not well supported by EDA tools. Modern integrated circuit design heavily depends on circuit-level SPICE simulators that integrate compact device models through modified nodal analysis (MNA) representation. This paper presents a novel MNA-based SPICE simulation method for ferroelectric device models, targeted at the design space exploration of FeRAM bitcells. Furthermore, this paper provides a co-design procedure for FeRAM bitcells and sense amplifiers via a comprehensive case study.