Stochastic computing is a promising technique for realizing high-performance computing owing to its extremely low hardware cost. However, the stochastic number (SN) has too many information redundancies, which leads to an exponential growth of latency. So, hybrid stochastic number (HSN) is proposed to solve the high-latency problem. Hybrid stochastic computing technology brings latency and efficiency advantages but faces the rigorous challenges of bit-width accumulation. In this study, a recoding method with high accuracy for HSN is proposed to reduce the bit width of HSN with only one clock delay. The hardware-resource savings in the polynomial circuit reach more than 80%. Then, the accuracy and fault tolerance of recoding are evaluated. The recoding method enables the pipeline structure in the pure HSN domain, preventing data conversion at the midpoint of the computation. Furthermore, based on the recoding method, a low-cost, bit-flip correction method for HSN is proposed, for realizing fault-tolerant data transmission and computation.

In this article, a signed-digit hybrid stochastic number (SD-HSN), which combines the two-line bipolar stochastic number (TLB-SN) and the binary signed-digit (BSD) number, is proposed and discussed. As a bipolar format hybrid stochastic number (SN), SD-HSN extends the concept of conventional TLB-SN to a signed-digit stochastic stream. The positional-weight-based TLB-SNs are still a stochastic stream with BSD, which is computed according to the arithmetic of its expectation with the redundant number method. The multiplication by SD-HSN shows a high-computational performance thanks to the redundant SD-HSN circuit. The efficient multiply-accumulate (MAC) is implemented by SD-HSN designs with low area and low-power consumption. The fault tolerance mechanism of SD-HSN is demonstrated by a JPEG image compression algorithm and a neural network. Besides, SD-HSN shows its advantage in hardware cost and power consumption over conventional BSD number multiplication and its high accuracy, high efficiency, and low latency compared to the classic stochastic computing (SC) methods. The SD-HSN circuits proposed, which include a generator, adder, and multiplier, are designed and implemented based on a standard 40-nm CMOS process.