Demo Data from EDBT 2026 / reviewers in the wild / expert
Ramin Izadpanah
dblp:183/4965
· DBLP profile ↗
5ranked-venue papers
3as first author
1since 2021 · last 2021
0000-0002-7253-084XORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 1 since 2021Computer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 57% Distributed systems · 19% Parallel and multicore computing · 19% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Distributed systems
concurrency control |
0.5 | 1 | 2021 | PETRA: Persistent Transactional Non-blocking Linked Data Structures · ACM Trans. Archit. Code Optim. 2021 |
Memory systems
non-volatile memory |
0.5 | 1 | 2021 | PETRA: Persistent Transactional Non-blocking Linked Data Structures · ACM Trans. Archit. Code Optim. 2021 |
Memory systems › non-volatile memory
persistent memory |
0.5 | 1 | 2021 | PETRA: Persistent Transactional Non-blocking Linked Data Structures · ACM Trans. Archit. Code Optim. 2021 |
Memory systems › non-volatile memory › persistent memory
persistent transactional memory |
0.5 | 1 | 2021 | PETRA: Persistent Transactional Non-blocking Linked Data Structures · ACM Trans. Archit. Code Optim. 2021 |
Parallel and multicore computing
transactional memory |
0.5 | 1 | 2021 | PETRA: Persistent Transactional Non-blocking Linked Data Structures · ACM Trans. Archit. Code Optim. 2021 |
Storage systems
crash recovery |
0.1 | 1 | 2021 | PETRA: Persistent Transactional Non-blocking Linked Data Structures · ACM Trans. Archit. Code Optim. 2021 |
Methods — techniques the papers use, named apart from their topics
software transactional memory · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | PETRA: Persistent Transactional Non-blocking Linked Data StructuresabstractEmerging byte-addressable Non-Volatile Memories (NVMs) enable persistent memory where process state can be recovered after crashes. To enable applications to rely on persistent data, durable data structures with failure-atomic operations have been proposed. However, they lack the ability to allow users to execute a sequence of operations as transactions. Meanwhile, persistent transactional memory (PTM) has been proposed by adding durability to Software Transactional Memory (STM). However, PTM suffers from high performance overheads and low scalability due to false aborts, logging, and ordering constraints on persistence. In this article, we propose PETRA, a new approach for constructing persistent transactional linked data structures. PETRA natively supports transactions, but unlike PTM, relies on the high-level information from the data structure semantics. This gives PETRA unique advantages in the form of high performance and high scalability. Our experimental results using various benchmarks demonstrate the scalability of PETRA in all workloads and transaction sizes. PETRA outperforms the state-of-the-art PTMs by an order of magnitude in transactions of size greater than one, and demonstrates superior performance in transactions of size one. Ramin Izadpanah, Christina L. Peterson, Yan Solihin, Damian Dechev |
ACM Trans. Archit. Code Optim. | 1 |
| 2020 | Towards workload-adaptive scheduling for HPC clustersabstractThe performance of HPC clusters depends on efficient scheduling of jobs. However, modern schedulers generally lack real-time information about resource utilization and require users to provide information, which is seldom accurate, on job requirements. The problem is exacerbated as HPC systems become increasingly more complicated and heterogeneous, which gives rise to new resource constraints (GPU, parallel file system, network bandwidth, burst buffers, etc.) In this work, we integrated data from LDMS, the Lightweight Distributed Metric Service, with Slurm, a popular job scheduler. To demonstrate the capabilities of such integration, we enabled scheduling based on the Lustre file system throughput. We demonstrated benefits of measurement of real-time utilization, prediction of applications requirements from historical data, and finer control of resources, in a preliminary evaluation of scheduling on a cluster of virtual machines. We also identified the possibility of further improving the scheduling efficiency through workload-adaptive scheduling, by adjusting the scheduling based on characteristics of the pending job. We validated the feasibility of this strategy by simulating job executions in our custom-made HPC cluster simulator. Alexander V. Goponenko, Ramin Izadpanah, Jim M. Brandt, Damian Dechev |
CLUSTER | 2 |
| 2018 | Integrating Low-latency Analysis into HPC System MonitoringabstractThe growth of High Performance Computer (HPC) systems increases the complexity with respect to understanding resource utilization, system management, and performance issues. While raw performance data is increasingly exposed at the component level, the usefulness of the data is dependent on the ability to do meaningful analysis on actionable timescales. However, current system monitoring infrastructures largely focus on data collection, with analysis performed off-system in post-processing mode. This increases the time required to provide analysis and feedback to a variety of consumers. Ramin Izadpanah, Nichamon Naksinehaboon, Jim M. Brandt, Ann C. Gentile, Damian Dechev |
ICPP | 1 |
| 2018 | An Efficient Latch-free Database Index Based on Multi-dimensional ListsabstractIn the interests of improving database performance, researchers have considered lock-free data structures for their attractive progress guarantees and scalability. This paper considers the performance of a recently developed lock-free structure, multi-dimensional list (MDList), used as a database index in SOS, a high-performance, object-oriented database. In our tests, we find that MDList outperforms the existing locking structures in multi-threaded workloads. This is the first known use of MDList as an index structure in databases. Kenneth Lamar, Ramin Izadpanah, Jim M. Brandt, Damian Dechev |
IPCCC | 2 |
| 2016 | A Methodology for Performance Analysis of Non-blocking Algorithms Using Hardware and Software MetricsabstractNon-blocking algorithms are a class of algorithms that provide guarantees of progress within a system. These progress guarantees come from the fine-grained synchronization techniques incorporated into their design. There are a number of various non-blocking designs and implementations of concurrent algorithms. However, trade-offs between performance and non-blocking algorithm design decisions are poorly understood. The most common method to measure the performance of non-blocking algorithms is to analyze the number of operations completed over a period of time. Unfortunately, this coarse-grained approach for performance analysis is unable to capture and explain many of the nuances of the behavior of non-blocking algorithms. This can result in a flawed perception of such algorithms, which may lead to a misguided use of them. This work provides a fine-grained approach for the analysis of the design and use of non-blocking algorithms. To support this analysis, we introduce a methodology that enables a user to simulate an application's use of an arbitrary non-blocking algorithm and extract insightful information from the performance results. To better understand the behavior of non-blocking algorithms, we present metrics to measure the effectiveness of the key synchronization and memory management techniques used in non-blocking algorithms. Our analysis combines these new metrics with several well-known hardware metrics to explain key behaviors and develop new insights. To demonstrate the effectiveness of the proposed methodology, we integrate it within the Tervel framework and analyzed Tervel's vector in various use cases. Our experiments show that helping mechanisms negatively impact throughput by increasing misaligned data cache accesses. Furthermore, by studying the correlations between different metrics, we are able to observe the effect of thread interference on the CPU instructions and instruction cache invalidation, and then link the decrease in work completed to this effect. In addition to the provided information, these metrics revealed implementation errors that did not affect correctness but caused increased thread congestion. Ramin Izadpanah, Steven D. Feldman, Damian Dechev |
ISORC | 1 |