IEEE Std. 1687 (IJTAG) introduces reconfigurable scan networks that implement an effective test access in highly complex designs. Designing an optimized network, that provides access to the instruments, meets the non-functional constraints, and preserves a minimized routing effort, area overhead and test access time, forms a non-trivial optimization problem. This paper tackles the IJTAG network topology design challenge by proposing an evolutionary approach to synthesize reconfigurable scan networks with optimized routing and area overhead while minimizing the overall test time.

Reconfigurable transistors are a new emerging type of device, which offer the promise to improve the resistance of electronic components against know-how theft. In order to enable a product development of such an emerging device, a cross-layer design enablement strategy is needed, as emerging technologies are not necessarily compatible withstandard tools used in the industry. In ‘CirroStrato’, we aim on the development of such a complete flow enabling CMOS co-integration of reconfigurable transistors, ranging from process adjustments, device modeling, library characterization, physical and logical synthesis up towards sophisticated hardware security tests. In this multi-partner-project (MPP) paper, our aim is to elucidate the overall design enablement flow, as well as current research challenges on the individual stages.

The high-volume manufacturing test ensures the production of defect-free devices, which is of utmost importance when dealing with safety-critical systems. Such a high-quality test requires a deliberately designed scan network to provide a time and cost-effective access to many on-chip components, as included in state-of-the-art chip designs. The IEEE 1687 Std. (IJTAG) has been introduced to tackle this challenge by adding programmable components that enables the design of reconfigurable scan networks. Although these networks reduce the test time by shortening the scan chains’ lengths, the reconfiguration process itself incurs an additional time overhead. This paper proposes a heuristic method for designing customized multi-power domain reconfigurable scan networks with a minimized overall reconfiguration time. More precisely, the proposed method exploits a-priori given non-functional properties of the system, such as the power characteristics and the instruments’ access requirements. For the first time, these non-functional properties are considered to synthesize a well-adjusted and highly efficient multi-power domain network. The experimental results show a considerable improvement over the reported benchmark networks.

Today, Integrated Circuits (ICs) manufactoring is distributed over various foundries, resulting in untrustworthy supply chains. Therefore, significant concerns about malicious intentions like intellectual property piracy of the fabricated ICs exist. Logic Locking (LL) is one well-known protection technique to improve the security of ICs. However, there are approaches to unlocking the circuit, like the SAT-based attack. Significant research has been done on thwarting the SAT-based attack by providing SAT-resilient LL. Nevertheless, these SAT-resilient LL approaches have an inherent structural footprint, yielding a high vulnerability to structural attacks. Recently, Polymorphic Logic Gates (PLGs) have been utilized to implement logic obfuscation by replacing gates. Reconfigurable Field Effect Transistors (RFETs) are a new emerging technology for implementing such PLGs due to their inherent camouflaging properties. This work proposes a novel technique for increasing SAT-resilience while introducing no structural weakness using those PLGs. In particular, based on the concept of an SAT-based attack, a procedure for determining the most SAT-resilient placement of LL-cells is developed. The experimental evaluation proves that the proposed hardening of the placement increases the SAT-resilience compared to a random placement while providing inherent camouflaging of RFET-cells.

LBIST has been proven to be an effective measure for reaching functional safety goals for automotive microcontrollers. Due to a large variety of recent innovative features, every customer can adjust LBIST settings in a way that fits their use case. The downside of these user-defined configurations is the handling of their golden signatures: Traditionally, they can be computed only with access to the gate-level netlist. This is typically not possible for MCU customers because a netlist contains protected IP, which cannot be disclosed to third parties.This paper proposes a digital twin of the LBIST functionality that can overcome this drawback. It is an executable model that can be delivered together with the product. As a result, for the first time, a customer can compute a golden signature without knowledge of the netlist or other support of the supplier. We prove the efficacy of the digital twin in an industrial environment on an automotive microcontroller.

The high distribution of the manufacturing of Integrated Circuits (ICs) over different foundries yields long and untrustworthy supply chains. Logic locking is one prominent protection technique against malicious usage and counterfeit. The emerging technology of Reconfigurable Field-Effect Transistors (RFETs) has recently been utilized to implement new polymorphic logic mechanisms to protect intellectual property. The mechanisms’ assessment is important to reinforce the newly introduced protection mechanism and, hence, avoid any weak logic structures. So far, approximate Hamming Distance-based assessment techniques have been used for determining the protection quality while considering combinatorial circuits only. This work proposes a novel method to assess the quality of the RFET-based logic locking structures for sequential circuits. In particular, formal techniques are orchestrated to analyze the circuit’s state space to determine whether any incorrect keys exist that unintentionally unlock and exhibit the circuit’s correct functional behavior. The experimental evaluation validates that the proposed scheme unveils weaknesses of the protection structure, which remain undetected when using existing techniques.

The integration of Design for Testability measures is strictly required when designing complex Integrated Circuits (ICs) to ensure that a good testability prevails in the resulting design. By this, a high-quality manufacturing test can be performed, giving a certain level of confidence that no defects have occurred during the manufacturing process, which potentially tamper with the functional behavior's correctness. However, a high-quality test implies large test data volume and high test application time, yielding high test costs. This effect is even more amplified when testing ICs for safety-critical applications like automotive systems or avionics, enforcing a zero-defect policy. Analogously, specific structures for the Design for Debug and Diagnosis are introduced since similar problems exist when debugging complex systems. Finally, the Design for Reliability is becoming increasingly important in applications like avionics since the introduced system has typically to deal with harsh environmental conditions and, hence, the IC has to exhibit a specific level of robustness to withstand. This paper proposes novel contributions to, in the end, pave the way for the next generation of IC, which can be successfully and reliably integrated even in safety-critical applications. In particular, this paper combines formal techniques, such as the Boolean satisfiability problem and bounded model checking, to propose (I) a novel test access mechanism with embedded compression including an optimization-based retargeting framework, (II) a new hybrid compression architecture to address compression aborts and (II) an effective fault detection mechanism for single transient faults. The proposed measures are evaluated by considering industrial-relevant benchmark candidates, demonstrating their effectiveness and showing that state-of-the-art techniques are outperformed.

Over the last years, the structure sizes of integrated circuits have significantly been decreased. This allows for the development of small, powerful, and energy-efficient circuits, as required for the challenging application scenarios like given in automotive or avionic systems. Nanometer scaled technology nodes are more vulnerable against transient faults, for instance, as induced by high radiation beams, potentially causing an erroneous behavior of the system. Different types of approaches have been proposed to increase the robustness of circuits against these faults, particularly for safety-critical applications. Such a countermeasure calculates, for instance, application-specific knowledge yielding a highly efficient fault detection mechanism that enhances the robustness significantly. Since these approaches invoke formal techniques for an advanced state analysis, a high computational effort is required, limiting the applicability for large circuit designs. This work addresses these shortcomings by combining an evolutionary algorithm with newly developed multi-objective optimization operators, deliberately designed for the state analysis of sequential circuits. The developed measures are all seamlessly integrated into one dedicated hardware module. By this, prototyping devices like field programmable gate arrays can be orchestrated during the regular circuit design flow to execute the proposed module to, in the end, benefit from an enormous hardware-acceleration. The experimental evaluation clearly proves that the presented method allows calculating application-specific knowledge effectively. More precisely, the run-time is reduced by more than 1,200X while retaining (or even improving) the efficacy of the resulting on-chip fault detection mechanism compared to state-of-the-art in terms of robustness enhancement and introduced hardware overhead.

The massive increase in computation power leads to a renaissance of supervised learning techniques, which were published decades ago but have so far been confined to theory. These techniques form the increasingly important field of Machine Learning (ML), which contributes to a large variety of research concerning industrial, automotive but also consumer applications strongly influencing our daily life. Commonly, the learning techniques require a set of labeled data, which involves a resource-intensive generation, to conduct the training. Depending on the dimensionality of the data and the required precision as needed by the application, the amount of training data varies. In case of insufficient training data, the prediction is of low-quality or not even possible at all, restricting the applicability of ML. This work proposes a combination of formal techniques and ML to implement a framework that allows coping with high-dimensional, training data while retaining a high prediction quality. The efficacy of this method is exemplarily demonstrated on the basis of an interdisciplinary material science research problem concerning the development of new structural materials, though it can be adapted to further applications.

Within the last decades, tremendous research work has been carried out on the development of software-based algorithms to solve the Boolean Satisfiability Problem. These SAT-solvers have then been heavily orchestrated for addressing complex computational tasks like the verification of circuits. In this field, most of the applied techniques focused only on the design phase of the circuit. Due to this fact, new approaches have been published in the literature solely focusing on online verification as well as self-verification. These kind of solutions strictly require Hardware (HW) SAT-solvers that can be integrated into a system while introducing only low hardware overhead and still providing high flexibility. By following these observations, this work presents SAT-Hard: In contrast to the state-of-the-art, SAT-Hard takes advantage of learning techniques to support features like clause learning and non-chronological backtracking, and combines them within a lightweight and standalone HW device. By this, a run-time speed-up of 2,000x can be achieved. Furthermore, the experimental evaluation clearly demonstrates that those complex problems can be solved in less than 20 seconds. Particularly due to its compactness, SAT-Hard is suitable for self-verification that enables the continuous verification of an integrated system during its lifetime.

This work presents a novel hybrid compression architecture that seamlessly combines the advantages of an embedded test compression technique with a lightweight codeword-based compression scheme. The proposed architecture tackles the shortcomings of state-of-the-art techniques, which are widely to address the rising challenges of safety-critical applications enforcing a zero defect policy. Embedded test compression techniques had been introduced that allow the compression of a large share of the test patterns. However, depending on the test application (e.g. low pin count test) there is a certain number of test patterns, which are incompressible due to the architecture and will be rejected. This leads to a test coverage decrease which, in turn, jeopardizes the zero defect policy. Therefore, the rejected test patterns are typically transferred in an uncompressed way bypassing the embedded compression, which is extremely costly. The proposed hybrid architecture mitigates the adverse impact of rejected test patterns on the compression ratio as well as on the test application time of state-of-the-art techniques. The experimental evaluation of industrial-sized designs clearly shows that a significant compression ratio up to 67.4 % and a test application time reduction up to 65.7% can be achieved.

This work presents a novel hybrid compression architecture that seamlessly combines the advantages of an embedded test compression technique with a lightweight codeword-based compression scheme. Embedded test compression has proven to be beneficial and is widely used in industrial circuit designs. However, particularly, in test applications within low-pin-count environments, a certain number of test patterns is incompressible and will, therefore, be rejected. This leads to a test coverage decrease which, in turn, jeopardizes the zero defect policy of safety-critical applications like automotive microcontrollers. Therefore, the rejected test patterns are typically transferred in an uncompressed way bypassing the embedded compression, which is extremely costly. The proposed hybrid architecture mitigates the adverse impact of rejected test patterns on the compression ratio as well as on the test application time of state-of-the-art techniques. The experimental evaluation of industrial-sized designs clearly shows that a significant compression ratio up to 67.4% and a test application time reduction up to 72.9% can be achieved when utilizing the existing multi-channel interfaces.

Due to their shrinking feature sizes as well as environmental influences, such as high-energy radiation, electrical noise, and particle strikes, integrated circuits are getting more vulnerable to transient faults. Accordingly, how to make those circuits more robust has become an essential step in today's design flows. Methods increasing the robustness of circuits against these faults already exist for a long period of time but either introduce huge additional logic, change the timing behavior of the circuit, or are applicable for dedicated circuits such as microprocessors only. In this paper, we propose an alternative method, which overcomes these drawbacks by determining application-specific knowledge of the circuit, namely the relations of flip-flops and when they assume the same value. By this, we exploit partial redundancies, which are inherent in most circuits anyway (even the optimized ones), to frequently compare the circuit signals for their correctness-eventually leading to an increased robustness. Since determining the correspondingly needed information is a computationally hard task, formal methods, such as bounded model checking, satisfiability-based automatic test pattern generation, and binary decision diagrams, are utilized for this purpose. The resulting methodology requires only a slight increase in additional hardware, does only influence the timing behavior of the circuit negligibly, and is automatically applicable to arbitrary circuits. Experimental evaluations confirm these benefits.

To close the ever widening verification gap, new powerful solutions are strictly required. One such promising approach aims in continuing verification tasks after production of a chip during its lifetime. This approach is called self-verification. However, for realizing self-verification tasks on-chip, verification packages have to be developed. In this paper, we propose verification package SAT-Lancer. SAT-Lancer is a compact Boolean Satisfiability (SAT) solver and has been implemented entirely on HW with the capability of solving any arbitrary SAT-instance. At the heart of SAT-Lancer is a scalable memory model, which can be adjusted to given memory constraints and allows to store the SAT-instance most effectively. In comparison to previous HW SAT-solvers, SAT-Lancer utilizes significant less area and can handle order of magnitude larger SAT-instances.

Due to shrinking feature sizes, integrated circuits are getting more vulnerable against transient faults. Methods increasing the robustness of circuits against these faults already exist for a long period of time but either introduce huge additional logic, increase the latency of the circuit, or are applicable for dedicated circuits such as microprocessors only. This work proposes an alternative hardening method which requires only a slight increase in additional hardware, does not influence the timing behavior, and is automatically applicable to arbitrary circuits. To this end, application-specific knowledge of the considered circuit is exploited, analyzed by a dedicated orchestration of formal techniques, and, eventually, used to synthesize a fault detection mechanism enhancing the robustness of the circuit. Experimental evaluations show that the proposed solution leads to a significant increase in the robustness, while the hardware overhead is kept moderate.

We present a formal optimization technique that enables retargeting for codeword-based IEEE 1149.1-compliant TAP controllers. The proposed method addresses the problem of high test data volume and Test Application Time (TAT) for a system-on-chip design during board or in-field testing, as well as during debugging. This procedure determines an optimal set of codewords with respect to given hardware constraints, e.g., embedded dictionary size and the interface to the Test Data Register in the IEEe 1149.1 Std. A complete traversal of the spanned search space is possible through the use of formal methods. An optimal set of codewords can be determined, which is directly utilized for retargeting. The proposed method is evaluated using test data with high-entropy, which is known to be the least amenable to compression, as well as input data for debugging and Functional Verification (FV) test data. Our results show a compression ratio improvement of more than 30% and a reduction in TAT up to 20% compared to previous techniques.

This work presents a new dynamically configurable compression architecture to be integrated directly into the test access mechanism of System-on-Chip (SoC) designs using IEEE 1149 compliant interfaces. The proposed technique reduces the test data volume without loosing the full legacy support, no extra IO pins are needed and the additional allocated hardware resources are negligible. Particularly, this technique is suitable for board as well as in-field testing, which both use typically a Test Access Mechanism (TAM) like IEEE 1149. Here, strong memory limitations exist on the test equipment, which restrict the testing or debugging capabilities for complex designs. Various benchmarks for random test data, representing highly pre-compressed test data, as well as fully-specified test data for selected industrial circuit designs were run and discussed to evaluate this new approach. These experiments clearly show a high test data volume reduction. Additionally, a noticeable reduction of the overall number of required test cycles are achieved for most of the test cases.