Wei-Chun Wang 0001

dblp:183/6062-1 · also Wei Chun Wang 0001 · DBLP profile ↗
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3ranked-venue papers
0as first author
3since 2021 · last 2026
0009-0004-5081-1730ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
YearPublicationVenuePosition
2026 A Top-Down Design Methodology for Accuracy-to-Noise Mapping in Analog Compute-in-Memory Systems: Evaluation on Mamba
Isha Chakraborty, Laith A. Shamieh, Wei-Chun Wang 0001, Han Cho, Saibal Mukhopadhyay
ISLPED3
2024 Cognitive Sensing for Energy-Efficient Edge Intelligence
abstract
Edge platforms in autonomous systems integrate multiple sensors to interpret their environment. The high-resolution and high-bandwidth pixel arrays of these sensors improve sensing quality but also generate a vast, and arguably unnecessary, volume of real-time data. This challenge, often referred to as the analog data deluge, hinders the deployment of high-quality sensors in resource-constrained environments. This paper discusses the concept of cognitive sensing, which learns to extract low-dimensional features directly from high-dimensional analog signals, thereby reducing both digitization power and generated data volume. First, we discuss design methods for analog-to-feature extraction (AFE) using mixed-signal compute-in-memory. We then present examples of cognitive sensing, incorporating signal processing or machine learning, for various sensing modalities including vision, Radar, and Infrared. Subsequently, we discuss the reliability challenges in cognitive sensing, taking into account hardware and algorithmic properties of AFE. The paper concludes with discussions on future research directions in this emerging field of cognitive sensors.
Minah Lee, Sudarshan Sharma, Wei-Chun Wang 0001, Hemant Kumawat, Nael Mizanur Rahman, Saibal Mukhopadhyay
DATE3
2024 Cryogenic Operation of Computing-In-Memory based Spiking Neural Network
abstract
This paper introduces a Computing-In-Memory based Spiking Neural Network (SNN) architecture for cryogenic operation of CMOS (Cryo-SNN). The paper demonstrates design strategies to improve energy efficiency of Cryo-SNN by coupling low-voltage operation at cryogenic temperature with innovative design of neuron circuits optimized for cryogenic conditions. By exploiting the enhanced device characteristics of 14 nm FinFET transistors at cryogenic temperatures, our architecture outlines critical adaptations to SNN components for optimal functionality in extreme environments. The circuit simulation using measurement calibrated 14nm FinFET models shows that a Cryo-SNN designed for MNIST classification operates with 4.54X improved energy-delay-product (EDP) over room temperature operation while maintaining similar accuracy. Further, the paper designs an optimized SNN architecture for autonomous health monitoring of miniaturized satellites at cryogenic temperature consuming less than 1mW of power.
Laith A. Shamieh, Wei-Chun Wang 0001, Shida Zhang, Rakshith Saligram, Amol D. Gaidhane, Yu Cao 0001, Arijit Raychowdhury, Suman Datta, Saibal Mukhopadhyay
ISLPED2