In the era of artificial intelligence (AI), deep neural networks (DNNs) have emerged as the most important and powerful AI technique. However, large DNN models are both storage and computation intensive, posing significant challenges for adopting DNNs in resource-constrained scenarios. Thus, model compression becomes a crucial technique to ensure wide deployment of DNNs.

Convolutional neural networks (CNNs) are widely used in various intelligent tasks. However, the huge computational complexity of CNNs makes it hard to be implemented in many real-time embedded devices. Various methods have been employed to reduce the model size of CNNs, where the Canonical Polyadic Decomposition (CPD) has shown its capability to reduce both the computational complexity and the storage requirement with negligible accuracy loss. In this paper, an efficient configurable hardware architecture called EadNet is proposed for CPD-CNNs. In detail, to minimize the on-chip memory access, different data reuse patterns are first analyzed. Based on the chosen optimal reuse scheme, a much improved computation flow is also developed for efficiently caching activations. The EadNet is implemented with a TSMC 90nm CMOS technology. The implementation results indicate that EadNet achieves considerable improvements on computation efficiency compared to the state-of-the-art CNN accelerator architectures.