Power supply voltage reduction is a primary enabler for sustaining the increasing demand for ultra-low power processors. On-die memories, which are traditionally implemented by SRAM, stop functioning properly when the supply voltage is scaled down aggressively; hence, embedded DRAM (eDRAM) bit-cells are used instead. These bit-cells leak their data strongly in one direction, whereas the leakage in the opposite direction is considerably lower. Due to their intrinsic limited Data Retention Time (DRT), these memories require power-hungry refreshing, which degrades performance. In an attempt to extend the DRT of a bit-cell, theoretically to infinity, compounds of various types of storage nodes in a single bit-cell, storing the datum and its complement, were examined here. A rigorous proof shows that under realistic leakage models, there is an inherent incompleteness preventing the proper readout and decision of the stored value after a certain time. Adopting the idea of dual-polarity complementary storage nodes, a new eDRAM self-refreshable bit-cell is proposed that yields a considerably extended DRT. The dual-polarity property enables the refreshing of an entire memory array in a single clock cycle, thus almost nullifying the unavoidable performance loss occurred by row-by-row ordinary power-hungry refreshing.

On-die memories, which are traditionally implemented by SRAM, stop functioning properly when the supply voltage is scaled down aggressively; hence, embedded DRAMs (eDRAMs) are used instead. Opportunistic refreshing was proved to eliminate the performance loss incurred by the eDRAM refreshing must. We show here that Gain-Cell eDRAM (GCeDRAM) supplemented with opportunistic refreshing consumes significantly smaller power and energy than SRAM. Analysis supported by hardware simulations demonstrate that the same design point achieves maximum performance and minimum energy. Replacement of the data memory in the ultra-low power processor PULPino from SRAM to opportunistically refreshed GCeDRAM yielded 30% energy savings in the memory, which translated into 7% savings in the entire processor.

Ultra-low power processors designed to work at very low voltage are the enablers of the internet of things (IoT) era. Their internal memories, which are usually implemented by a static random access memory (SRAM) technology, stop functioning properly at low voltage. Some recent commercial products have replaced SRAM with embedded memory (eDRAM), in which stored data are destroyed overtime, thus requiring periodic refreshing that causes performance loss. This article presents a queuing-based opportunistic refreshing algorithm that eliminates most if not all of the performance loss and is shown to be optimal. The queues used for refreshing miss refreshing opportunities not only when they are saturated but also when they are empty, hence increasing the probability of performance loss. We examine the optimal policy for handling a saturated and empty queue, and the ways in which system performance depends on queue capacity and memory size. This analysis results in a closed-form performance expression capturing read/write probabilities, memory size and queue capacity leading to CPU-internal memory architecture optimization.