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Soham Sinha 0001

dblp:183/8356-1 · DBLP profile ↗
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6ranked-venue papers
3as first author
4since 2021 · last 2025
0000-0001-8962-4714ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author · 2 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Embedded and real-time systems · 59% Parallel and multicore computing · 30% Electronic design automation · 11%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › dataflow computing
dataflow scheduling
1.622025
Faster, Exact, More General Response-Time Analysis for NVIDIA Holoscan Applications · RTSS 2025
Response-Time Analysis of a Soft Real-time NVIDIA Holoscan Application · RTSS 2024
Embedded and real-time systems
real-time scheduling
1.622025
Faster, Exact, More General Response-Time Analysis for NVIDIA Holoscan Applications · RTSS 2025
Response-Time Analysis of a Soft Real-time NVIDIA Holoscan Application · RTSS 2024
Embedded and real-time systems › real-time scheduling › schedulability analysis
response time analysis
1.622025
Faster, Exact, More General Response-Time Analysis for NVIDIA Holoscan Applications · RTSS 2025
Response-Time Analysis of a Soft Real-time NVIDIA Holoscan Application · RTSS 2024
Electronic design automation › timing analysis
end-to-end latency analysis
0.912025
Faster, Exact, More General Response-Time Analysis for NVIDIA Holoscan Applications · RTSS 2025
Embedded and real-time systems › model-based design › dataflow modeling
synchronous dataflow
0.912025
Faster, Exact, More General Response-Time Analysis for NVIDIA Holoscan Applications · RTSS 2025
Parallel and multicore computing › task scheduling
DAG scheduling
0.812024
Response-Time Analysis of a Soft Real-time NVIDIA Holoscan Application · RTSS 2024
Embedded and real-time systems
soft real-time systems
0.522025
Faster, Exact, More General Response-Time Analysis for NVIDIA Holoscan Applications · RTSS 2025
Response-Time Analysis of a Soft Real-time NVIDIA Holoscan Application · RTSS 2024

Methods — techniques the papers use, named apart from their topics

model checking · 0.9homogeneous synchronous dataflow graphs · 0.9static timing analysis · 0.8
YearPublicationVenuePosition
2025 Faster, Exact, More General Response-Time Analysis for NVIDIA Holoscan Applications
abstract
We present a scalable method to compute exact worst-case end-to-end latency in applications built on the NVIDIA Holoscan SDK, a framework increasingly adopted for soft real-time ML workloads in medical devices, surgical instruments, and robotics. Holoscan applications are structured as directed acyclic graphs of non-preemptible task threads (operators) connected by FIFO queues, where execution depends not only on input availability but also on downstream buffer capacity - an atypical backpressure mechanism not captured by standard dataflow or middleware models. Existing analyses either lack convergence guarantees or rely on restrictive assumptions (e.g., fixed execution times, unit-sized buffers), resulting in overly conservative bounds. We show that Holoscan's scheduling semantics can be faithfully reduced to homogeneous synchronous dataflow graphs (HSDFGs), enabling exact end-to-end latency analysis. Building on this insight, we introduce a dynamic algorithm that computes tight upper bounds on response time across infinite input streams under variable task runtimes and arbitrary buffer sizes. We prove its correctness and convergence, and demonstrate that it outperforms HSDFG model checking with UPPAAL in runtime while avoiding the pessimism of prior Holoscan-specific analyses. Experiments on real Holoscan applications from NVIDIA HoloHub and large synthetic graphs confirm its scalability and precision.
Philip Schowitz, Shubhaankar Sharma, Siddharth Balodi, Soham Sinha 0001, Bruce Shepherd, Arpan Gujarati
RTSS4
2024 Response-Time Analysis of a Soft Real-time NVIDIA Holoscan Application
abstract
NVIDIA Holoscan SDK is a novel edge and embedded software development framework designed for NVIDIA System-on-Chips (SoCs), primarily targeting medical device applications. This SDK facilitates complex data processing workflows using Directed Acyclic Graphs (DAGs) composed of functional units termed operators. These operators, running in separate threads, are usually interconnected with intricate execution dependencies influenced by both upstream and downstream conditions on communication data buffers. Current methods to measure the response time of a complex Holoscan application rely on empirical benchmarking, which can be costly, time-consuming, and unreliable – limitations that are particularly critical in sectors where safety and certification concerns are paramount. This paper introduces a novel static analysis methodology to determine worst-case end-to-end response times in NVIDIA Holoscan applications. Our approach overcomes the drawbacks of existing empirical tools by providing a response-time analysis capable of handling complex operator interactions and communication buffering mechanisms inherent in Holoscan’s architecture. Through rigorous theoretical analysis and empirical validation, our method not only ensures predictability in system behavior but also aids developers in identifying performance bottlenecks and optimizing system design. Evaluation using real-world NVIDIA HoloHub applications demonstrates the efficiency and accuracy of our analysis, achieving theoretical response times as close as $0.3 \%$ of empirically measured numbers on NVIDIA hardware using less than 1ms computation time.
Philip Schowitz, Soham Sinha 0001, Arpan Gujarati
RTSS2
2022 ModelMap: A Model-Based Multi-Domain Application Framework for Centralized Automotive Systems
abstract
This paper presents ModelMap, a model-based multi-domain application development framework for DriveOS, our in-house centralized vehicle management software system. DriveOS runs on multicore x86 machines and uses hardware virtualization to host isolated RTOS and Linux guest OS sandboxes. In this work, we design Simulink interfaces for model-based vehicle control function development across multiple sandboxed domains in DriveOS. ModelMap provides abstractions to: (1) automatically generate periodic tasks bound to threads in different OS domains, (2) establish cross-domain synchronous and asynchronous communication interfaces, and (3) handle USB-based CAN I/O in Simulink. We introduce the concept of a nested binary, for the deployment of ELF binary executable code in different sandboxed domains. We demonstrate ModelMap using a combination of synthetic benchmarks, and experiments with Simulink models of a CAN Gateway and HVAC service running on an electric car. ModelMap eases the development of applications, which are shown to achieve industry-target performance using a multicore hardware platform in DriveOS.
Soham Sinha 0001, Anam Farrukh, Richard West
ICCAD1
2021 Towards an Integrated Vehicle Management System in DriveOS
abstract
Modern automotive systems feature dozens of electronic control units (ECUs) for chassis, body and powertrain functions. These systems are costly and inflexible to upgrade, requiring ever increasing numbers of ECUs to support new features such as advanced driver assistance (ADAS), autonomous technologies, and infotainment. To counter these challenges, we propose DriveOS, a safe, secure, extensible, and timing-predictable system for modern vehicle management in a centralized platform. DriveOS is based on a separation kernel, where timing and safety-critical ECU functions are implemented in a real-time OS (RTOS) alongside non-critical software in Linux or Android. The system enforces the separation, or partitioning, of both software and hardware among different OSes. DriveOS runs on a relatively low-cost embedded PC-class platform, supporting multiple cores and hardware virtualization capabilities. Instrument cluster, in-vehicle infotainment and advanced driver assistance system services are implemented in a Yocto Linux guest, which communicates with critical real-time services via secure shared memory. The RTOS manages a real-time controller area network (CAN) interface that is inaccessible to Linux services except via well-defined and legitimate communication channels. In this work, we integrate three Qt-based services written for Yocto Linux, running in parallel with a real-time longitudinal controller task and multiple CAN bus concentrators, for vehicular sensor data processing and actuation. We demonstrate the benefits and performance of DriveOS with a hardware-in-the-loop CARLA simulation using a real car dataset.
Soham Sinha 0001, Richard West
ACM Trans. Embed. Comput. Syst.1
2020 PAStime: Progress-Aware Scheduling for Time-Critical Computing
abstract
Over-estimation of worst-case execution times (WCETs) of real-time tasks leads to poor resource utilization. In a mixed-criticality system (MCS), the over-provisioning of CPU time to accommodate the WCETs of highly critical tasks may lead to degraded service for less critical tasks. In this paper we present PAStime, a novel approach to monitor and adapt the runtime progress of highly time-critical applications, to allow for improved service to lower criticality tasks. In PAStime, CPU time is allocated to time-critical tasks according to the delays they experience as they progress through their control flow graphs. This ensures that as much time as possible is made available to improve the Quality-of-Service of less critical tasks, while high-criticality tasks are compensated after their delays. This paper describes the integration of PAStime with Adaptive Mixed-criticality (AMC) scheduling. The LO-mode budget of a high-criticality task is adjusted according to the delay observed at execution checkpoints. This is the first implementation of AMC in the scheduling framework of LITMUS^RT, which is extended with our PAStime runtime policy and tested with real-time Linux applications such as object classification and detection. We observe in our experimental evaluation that AMC-PAStime significantly improves the utilization of the low-criticality tasks while guaranteeing service to high-criticality tasks.
Soham Sinha 0001, Richard West, Ahmad Golchin
ECRTS1
2020 Boomerang: Real-Time I/O Meets Legacy Systems
abstract
This paper presents Boomerang, an I/O system that integrates a legacy non-real-time OS with one that is customized for timing-sensitive tasks. A relatively small RTOS benefits from the pre-existing libraries, drivers and services of the legacy system. Additionally, timing-critical tasks are isolated from less critical tasks by securely partitioning machine resources among the separate OSes. Boomerang guarantees end-to-end processing delays on input data that requires outputs to be generated within specific time bounds.We show how to construct composable task pipelines in Boomerang that combine functionality spanning a custom RTOS and a legacy Linux system. By dedicating time-critical I/O to the RTOS, we ensure that complementary services provided by Linux are sufficiently predictable to meet end-to-end service guarantees. While Boomerang benefits from spatial isolation, it also outperforms a standalone Linux system using deadline-based CPU reservations for pipeline tasks. We also show how Boomerang outperforms a virtualized system called ACRN, designed for automotive systems.
Ahmad Golchin, Soham Sinha 0001, Richard West
RTAS2