The widespread application of specialized embedded devices and their ever-growing sensing capabilities lead to an overload of raw data reaching the Cloud via the Internet of Things. Despite this massive amount of available data, data-driven applications still produce a limited impact on the real world. We argue that this limitation arises from the complexity the developers still face when engineering and deploying solutions on a plurality of embedded devices. Instead of focusing on constructing valuable information from raw data and designing algorithms to exploit it, the developers still have to figure out on their own: how to partition the computation between Edge, Fog, and Cloud; how to move partial results around in highly distributed solutions; how to create abstract interfaces to expose information-rich endpoints. This paper introduces the Virtual Sensor Domain-Specific Language (DSL), which builds the keystone for designing and developing powerful Computer-Aided Design tools and Integrated Development Environments to support the developers in focusing on information manipulation. The Virtual Sensor DSL is built on top of C++ to ease its adoption by the embedded development community. It introduces a reactive approach to data collection, technology mapping, and workload distribution. It allows the creation of adaptable Virtual Sensors, streaming processed information coming from the integration of multiple raw data streams, and it comes with integrated simulation capabilities, supporting prototyping. In this paper, we describe the entities the language offers, how the developers can exploit them, and analyze a real-world use case that benefitted from the Virtual Sensor DSL.

With reconfigurable fabrics delivering increasing performance over the years, Field-Programmable Gate Arrays (FPGAs) are becoming an appealing solution for next-generation High-Performance Computing (HPC) systems. However, in order to gain traction among traditional von Neumann architectures, the optimization process of Field-Programmable Gate Array (FPGA) designs should be further abstracted to a higher level. In fact, while High-Level Synthesis (HLS) already provides a handy way to write FPGA code with common high-level languages, substantial effort and expertise are still required to optimize the resulting FPGA design for the underlying hardware. To overcome this problem, we propose a semi-automated performance optimization methodology based on a Hierarchical Roofline model for FPGAs. System-wide and applications-specific optimizations such as off-chip memory transfer and data locality optimizations are guided by the FPGA Roofline model whereas FPGA-specific optimizations are automatically searched by a Design Space Exploration (DSE) engine. We demonstrate the way this methodology allows to easily analyze and optimize to peak system performance a wide set of applications ranging from particle methods, wavefront algorithms, and sparse arithmetic computations. In addition, we prove that the integrated Design Space Exploration (DSE) engine achieves a 14.36x maximum speedup if compared to previous automated solutions in the literature.

Pairwise sequence alignment accounts for the majority of key genome analysis applications' runtime. Because of the quadratic time complexity of exact alignment algorithms, the community is moving away from exact algorithms in favor of heuristics that only compute high-quality results. However, the state of the art lacks hardware-accelerated versions of these heuristic algorithms as the vast majority of the available solutions still rely on implementing exact alignment algorithms. Moreover, hardware-based implementations lack high-level APIs that can simplify their integration in commonly used genomic pipelines, hindering their applicability in real-world scenarios. In this context, we present the first high-performance FPGA implementation of the popular X-drop heuristic alignment algorithm and provide an easy-to-use API for its integration. On a Xilinx Alveo U280, our FPGA design achieves up to 5× speed-up over SeqAn, the state-of-the-art software version of the algorithm, running on two Intel Xeon processors using 80 CPU threads. Moreover, our design is also 3.45× faster than ksw2, a state-of-the-art vectorized alignment algorithm that performs a similar heuristic to the one employed in the X-drop algorithm. Finally, our implementation also outperforms LOGAN, a recently published GPU implementation of X-drop running on an Nvidia Tesla V100, by a factor of 1.5×.

The intrinsic complexity of modern computing systems requires structured methods for analyzing and optimizing application performance. In this context, the Roofline model proposes an intuitive and visual method providing performance insight and optimization guidance for a given architecture. Although this methodology successfully models multicore and GPU performance optimizations, the original formulation does not directly apply to FPGA devices. For this reason, we propose a Roofline model analysis for reconfigurable architectures and an associated CAD tool for assisting HLS optimization of C/C++ applications. We firstly model FPGA attainable performance by means of an analytical method. Then, we integrate locality walls and a DSE engine for an enhanced optimization process. Starting from a software version of the N-body algorithm, we firstly illustrate how our methodology helps at quickly achieving performance comparable to a state-of-the-art FPGA bespoke implementation. Then, we illustrate an assisted platform porting of the Smith-Waterman sequence alignment providing a 9x speedup. Finally, we evaluated the single DSE engine on the Poly-Bench test suite and achieved performance improvements up to 14.36x compared to previous automated solutions in the literature.

The acceleration of compute-intensive applications on FPGA-based systems has become an increasingly common trend thanks to their availability as cloud commodities. This trend has also been accompanied by wider support of High-Level Synthesis tools. Despite these solutions reduce the learning curve for hardware development, the programmer still requires specific expertise in order to achieve efficient implementations. In this paper, we propose an automated approach for the acceleration of C applications into dataflow kernels on FPGAs.

The growing interest in FPGA-based solutions for accelerating compute demanding algorithms is pushing the need for new tools and methods to improve productivity. In this work, we propose a methodology to support designers in generating optimal FPGA hardware implementations using High-Level Synthesis (HLS). First, we propose an automated roofline model generation that operates directly on a C/C++ description of the algorithm. The approach enables fast evaluation of the operational intensity of the target function and visualizes the main bottlenecks of the current HLS implementation, providing guidance on how to improve it. Second, we integrate it with a Design Space Exploration (DSE) methodology for quickly evaluating different HLS directives to identify an optimal implementation.

In the current years broad access to genomic data is leading to improve the understanding and prevention of human diseases as never before. De-novo genome assembly, represents a main obstacle to perform the analysis on a large scale, as it is one of the most time-consuming phases of the genome analysis. In this paper, we present a scalable, high performance and energy efficient architecture for the alignment step of SSPACE, a state of the art tool used to perform scaffolding also in case of de-novo assembly. The final architecture is able to achieve up to 9.83x speedup in performance when compared to the software version of Bowtie, a state of the art tool used by SSPACE to perform the alignment.

The 5-point relative pose problem is to identify the possible relative camera motions given five matching points from two calibrated views. Several algorithms for solving this problem have been presented in the literature providing different tradeoffs in terms of computational complexity and accuracy of the results. Indeed, the research in this field is driven mostly by the need for accurate solutions and high performance to cope with real-time requirements. In this work we propose an implementation to solve the 5-point relative pose problem accelerated on Field Programmable Gate Array (FPGA). The proposed architecture implements the classical Nister's algorithm as a deep pipeline deployed on a AWS F1 instance and outperforms software implementations by a factor ranging from 7.2X to 233X. Furthermore, it achieves a speedup of 64.2X compared to the Nister's software implementation with comparable accuracy.

One of the main objectives of human genetic research is the identification of DNA variations that may be involved in the development of rare diseases. Thanks to advances in DNA sequencing technologies and to a progressive integration of the available genetic databases, it is now possible to study not only common variants, but also ones occurring at very low frequencies in the population. Despite the presence of consolidated algorithms to perform the analysis of genetic data, the major hurdle is the impossibility to efficiently process the data, and translate them into biologically meaningful information. This prevents the current solutions and architectures from scaling to growing number of individuals, both for the discovery of new variants and the adoption of these methodologies to support diagnosis and treatment of illnesses in a common clinical setting. In this scenario, Field Programmable Gate Arrays (FPGAs) provide a viable alternative to conventional software-based approaches. In particular, they have already proved to efficiently manage huge workloads while reaching outstanding performance over power consumption scores. Therefore, the purpose of this work is exploring novel computing paradigms to tackle the limitations we are facing. In particular, we present an FPGA-based acceleration of the PairHMM Forward Algorithm, the performance bottleneck in the HaplotypeCaller, a variant calling tool in the popular Genome Analysis Toolkit (GATK). Our final architecture is able to achieve 2160x speedup when compared to the Original Java version in GATK, outperforming existing implementation on both CPUs, GPUs and FPGAs.

The N-Body simulation process describes the evolution of a system of forces composed of N bodies, which may represent celestial objects, molecules, and so on. The most accurate algorithm for N-Body simulation, the All-Pairs method, is particularly compute intensive and software implementations on CPUs are inefficient in terms of performance and power consumption. An implementation on a hardware accelerator, such as an FPGA, would benefits in both these terms, exploiting a parallel execution at a relative low power profile. Moreover, it would also benefit faster methods with lower computational complexity, since many of them rely on the All-Pairs approach to approximate the calculation of forces. This work proposes a highly scalable, power efficient and high performance hardware architecture for the N-Body All-Pairs simulation problem. Our final implementation is able to scale up to systems with an arbitrary number of bodies thanks to a tiling approach that allows performance in the order of 13,441 MPairs/s, outperforming state of the art implementations on FPGA in terms of both pure performance, as well as performance per watt ratio. Finally, our design results to be more power efficient than Grape-8 ASIC.

The goal of reaching exascale computing is made especially challenging by the highly heterogeneous nature of modern platforms and the energy they consume. As compute nodes typically utilize multiple multi-core CPU and are increasingly equipped with PCIe based accelerators, both are contributing to an ever more dynamic power consumption. In our study we evaluate our target application on a variety of heterogeneous platforms, including high end FPGA, GPU, and Xeon Phi accelerators, with respect to energy efficiency at a node and cluster level. We compare multiple implementations of our application, each built with a different modern parallel programming framework, with respect to execution performance, code complexity and energy efficiency. Later we extrapolate based on our findings, the implications of scaling this application towards exascale, with projections of computation achievable within the exascale power budget for our three architectures.

Smith-Waterman is a dynamic programming algorithm that plays a key role in the modern genomics pipeline as it is guaranteed to find the optimal local alignment between two strings of data. The state of the art presents many hardware acceleration solutions that have been implemented in order to exploit the high degree of parallelism available in this algorithm. The majority of these implementations use heuristics to increase the performance of the system at the expense of the accuracy of the result. In this work, we present an implementation of the pure version of the algorithm. We include the key architectural optimizations to achieve highest possible performance for a given platform and leverage the Berkeley roofline model to track the performance and guide the optimizations. To achieve scalability, our custom design comprises of systolic arrays, data compression features and shift registers, while a custom port mapping strategy aims to maximize performance. Our designs are built leveraging an OpenCL-based design entry, namely Xilinx SDAccel, in conjunction with a Xilinx Virtex 7 and Kintex Ultrascale platform. Our final design achieves a performance of 42.47 GCUPS (giga cell updates per second) with an energy efficiency of 1.6988 GCUPS/W. This represents an improvement of 1.72x in performance and energy efficiency over previously published FPGA implementations and 8.49x better in energy efficiency over comparable GPU implementations.

In the context of heterogneous computing, even though GPUs are the components of election due to both their intrinsically parallel nature and their flexibility, FPGAs are being investigated and experimented due to superior power efficiency on selected workloads While GPUs are the heterogeneous components of election due to both their intrinsically parallel nature and their flexibility, FPGAs are being investigated and experimented due to superior power efficiency on selected workloads. However, the lack of adequate languages, runtimes, programming flexibility and, broadly speaking, proven system level approaches for FPGA-accelerated applications are the most relevant limiting factors to the adoption of these devices into mainstream. In these regards, Amazon recently released Amazon Web Services (AWS) EC2 F1, which are compute instances that are equipped with Xilinx FPGA boards. On such instances, the user can develop algorithms and run them on FPGAs thanks to the new software developed by Xilinx called SDAccel. In this paper, we describe how we extended the CAOS framework to integrate with SDAccel and target AWS F1 instances for improving the performance of a custom application by means of FPGA acceleration. We then propose a case study to test the new methodology, based on the N-Body Simulation problem. Results show that we were able to achieve performance comparable to the ones obtained by expert users in less than a day of work.