Bypass capacitances bridge the gap between momentary surges of power demand caused by switching transistors and the ability of power supplies to respond to these surges. Even though bypass capacitances are not explicitly specified in FPGA architectural specifications, the gate capacitances of quiescent transistors in an FPGA architecture can act as symbiotic bypass capacitances. Since any additional dedicated bypass capacitances can increase the implementation area of an FPGA, it is important to measure the ability of the quiescent bypass capacitances in maintaining stable operating voltages while the FPGA is powered by voltage sources with limited power outputs. This work measures the ability of the quiescent bypass capacitances in maintaining stable supply voltages under limited power in the context of FPGA architectural investigations. We found that, for the 12-LUT logic cluster investigated in this work, to limit VDD value droop to 5% of the nominal VDD value, the power source must be able to produce 3 times of the average power consumed by the same logic cluster powered by an ideal voltage source. When the power output is further reduced, VDD value droop increases, resulting in significantly increased delay and reduced noise margin. In addition, the degree of parallel execution also has a significant effect on VDD value. In particular, at the nominal VDD value of 0.9 volts and the maximum power output of 28.1 uW, executing all 12 LUTs in parallel results in VDD value drooping to a minimum value of 0.370 volts while executing 1 LUT at a time results in VDD value drooping to a minimum of 0.690 volts, with both cases achieving similar computing time. These results suggest that FPGA architectural evaluations should take bypass capacitances and the power limit of voltage sources into consideration in order to design efficient FPGA architectures for low power applications.

A new area model for estimating the layout area of switch blocks is introduced in this work. The model not only takes into consideration the active area that is needed to construct a switch block but also the number of metal layers available and the actual dimension of these metals. The model assigns metal layers to the routing tracks in a way that reduces the number of vias that are needed to connect different routing tracks together while maintaining the tile-based structure of FPGAs. The model is evaluated based on the layouts constructed in ASAP7 FinFET 7nm Predictive Design Kit. We found that the new model improves upon the traditional active-based area estimation models by considering the growth of metal area independently from the growth of the active area. As a result, the new model is able to more accurately estimate layout area by predicting when metal area will overtake active area as the number of routing tracks is increased. This ability allows the more accurate estimation of the true layout cost of FPGA fabrics at the early floor planning and architectural exploration stage; and this increase in accuracy can encourage a wider use of custom FPGA fabrics that target specific sets of benchmarks in future SOC designs.

This work presents the layout area of encoded and decoded multiplexers, two essential building blocks of modern FPGAs, in FinFET. Layouts with both 2 and 3 metal layers based on ASAP7 Predictive Design Kit are presented. The layout area is then compared with the prediction of two equation-based models: the VPR area model and the COFFE area model. We found that, with the original model parameters which are adjusted for planar technologies, these two equation-based models are not accurate in predicting FinFET layout area with error ranges of -2.3% to +86.5% and -32.7% to +19.3% for the VPR and COFFE models, respectively. Furthermore, when the model parameters are specifically adjusted for FinFET, the error ranges remain to be large with -19% to +31% and -26.6% to +25% for the VPR and COFFE models, respectively. These data underline the importance of verifying equation-based models against actual layout areas in FPGA architectural studies, especially when there are significant changes in the underlining process technologies.