This paper describes a low power digitizer for 3D-stacked high dynamic range (HDR) CMOS image sensors (CIS). It digitizes the electrical output signals from the pixel array on the upper chip in the 3-D-stacked CIS. It consists of a single-slope analog-to-digital converters (ADC) array with a comparator array and a digital counter array. To improve the power-efficiency of the HDR image generation systems, a piecewise-linear counting technique for an intra-scene dual-conversion gain (i-DCG) methodology is proposed. To optimize the power consumption of the ADC array, a decision-feedback technique and a hybrid counter structure are utilized in the comparator array and the counter array, respectively. With the proposed digitizer architecture, the ADC consumes only 22.8$\mu \mathbf{W}/\mathbf{column}$, which is remarkably power-efficient. Implemented in a 28 nm process technology, the proof-of-concept prototype achieves a random noise (RN) of 89$\mu \mathbf{V}$, a column fixed-pattern noise (FPN) of 6.5 ppm, and an integrated nonlinearity (INL) of 2 ppm at the analog gain of 16.

This paper describes a 108 mega pixels (Mp) CMOS image sensor (CIS) for mobile phone applications. The 0.7 $\mu$m-pitch pixel array ($12000\times 9000$) is composed of nona-cell ($3\times 3$ unit pixel structure) cluster with binning capability for maximum light absorption. In considerations of the trade-off between area occupation and frame rate, the column-parallel topology with thousands of single-slope ADCs is chosen for the digitizer. To suppress the horizontal noise (HN) source, an ADC decision-feedback technique is proposed to minimize the current consumption difference between before and after the ADC decision. Furthermore, with the decision-feedback loop, which is implemented in each of the comparators of the ADC array, analog power consumption can be also reduced. Top pixel and bottom digitizer chips were fabricated in 65 nm and 28 nm process technologies, respectively. The measurement results of the 3-D stacked prototype imager show an input-referred random noise (RN) of 1.4 $\mathrm{e}_{\mathrm{rms}}^{-}$ with an analog gain of 16 and a frame rate of 10 fps. A suppressed RN of 0.44 $\mathrm{e}_{\mathrm{rms}}^{-}$ is also achieved with a nona-binning. The column fixed-pattern noise (FPN) of the 108 MP imager is only 66 ppm. The high-resolution image sensing system with the decision-feedback technique achieves a figure-of-merit (FoM) of 0.71 e.nJ.

This paper describes a 16-bit incremental analog-to-digital converter (ADC) for sensor applications. To implement a wide applicable ADC, which can be used in the commercial case, a full-on-chip voltage reference for the delta-sigma (ΔΣ) ADC is incorporated. The swapping digital-to-analog converter (DAC) is proposed in the loop-filter to minimize the noise effect of the voltage reference, which can directly deteriorate the effective resolution (ER) of the readout system. Furthermore, gain programmable characteristic is embedded in the ADC for various applications. Measurements show that the ADC achieves 16.07-bit ER and 10 LSB integral nonlinearity (INL), while dissipating only 18 μA current from a 3.3 V supply. The ADC was fabricated in a 0.18-μm standard CMOS process with a 0.182 mm2active area.

A power-efficient programmable-gain control function embedded Delta-Sigma (ΔΣ) analog-to-digital converter (ADC) for various smart sensor applications is presented. It consists of a programmable-gain switched-capacitor ΔΣ modulator followed by a digital decimation filter for down-sampling. The programmable function is realized with programmable coefficients of a loop filter using a capacitor array. The coefficient control is accomplished with keeping the location of poles of a noise transfer function, so the stability of a designed closed-loop transfer function can be assured. The proposed gain control method helps ADC to optimize its performance with varying input signal magnitude. The gain controllability requires negligible additional energy consuming or area occupying block. The power efficient programmable-gain ADC (PGADC) is well-suited for sensor devices. The gain amplification can be optimized from 0 to 18 dB with a 6 dB step. Measurements show that the PGADC achieves 15.2-bit resolution and 12.4-bit noise free resolution with 99.9 % reliability. The chip operates with a 3.3 V analog supply and a 1.8 V digital supply, while consuming only 97 μA analog current and 37 μA digital current. The analog core area is 0.064 mm2 in a standard 0.18-μm CMOS process.