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Vijay Victor D'Silva

dblp:184/4036 · DBLP profile ↗
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16ranked-venue papers
11as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 13 · 10 first-authorTheory of computation · 3Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
4 papers
Program analysis · 73% Program verification · 27%
Theoretical computer science
3 papers
Automated reasoning and model checking · 86% Logic in computer science · 14%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Program analysis › static analysis
abstract interpretation
0.632017
Abstract Interpretation with Unfoldings · CAV (2) 2017
Abstract satisfaction · POPL 2014
Abstract conflict driven learning · POPL 2013
Automated reasoning and model checking
satisfiability
0.422014
Abstract satisfaction · POPL 2014
Abstract conflict driven learning · POPL 2013
Automated reasoning and model checking › satisfiability › SAT solving
conflict-driven clause learning
0.212013
Abstract conflict driven learning · POPL 2013
Logic in computer science › concurrency theory
unfolding
0.112017
Abstract Interpretation with Unfoldings · CAV (2) 2017
Program verification › model checking
bounded model checking
0.112008
A Survey of Automated Techniques for Formal Software Verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Program verification
model checking
0.112008
A Survey of Automated Techniques for Formal Software Verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Program analysis
static analysis
0.012008
A Survey of Automated Techniques for Formal Software Verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008

Methods — techniques the papers use, named apart from their topics

abstract interpretation · 0.7unfolding · 0.6quantification transformers · 0.4deduction transformers · 0.4abduction transformers · 0.4DPLL · 0.4underapproximation of least fixed points · 0.3overapproximation of greatest fixed points · 0.3implication graphs · 0.2implication graph · 0.2bounded model checking · 0.1
YearPublicationVenuePosition
2017 Abstract Interpretation with Unfoldings
Marcelo Sousa, César Rodríguez, Vijay Victor D'Silva, Daniel Kroening
CAV (2)3
2017 Independence Abstractions and Models of Concurrency
Vijay Victor D'Silva, Daniel Kroening, Marcelo Sousa
VMCAI1
2017 Complete Abstractions and Subclassical Modal Logics
Vijay Victor D'Silva, Marcelo Sousa
VMCAI1
2014 Abstract satisfaction
abstract
This article introduces an abstract interpretation framework that codifies the operations in SAT and SMT solvers in terms of lattices, transformers and fixed points. We develop the idea that a formula denotes a set of models in a universe of structures. This set of models has characterizations as fixed points of deduction, abduction and quantification transformers. A wide range of satisfiability procedures can be understood as computing and refining approximations of such fixed points. These include procedures in the DPLL family, those for preprocessing and inprocessing in SAT solvers, decision procedures for equality logics, weak arithmetics, and procedures for approximate quantification. Our framework provides a unified, mathematical basis for studying and combining program analysis and satisfiability procedures. A practical benefit of our work is a new, logic-agnostic architecture for implementing solvers.
Vijay Victor D'Silva, Leopold Haller, Daniel Kroening
POPL1
2014 Deciding floating-point logic with abstract conflict driven clause learning
abstract
We present a bit-precise decision procedure for the theory of floating-point arithmetic. The core of our approach is a non-trivial, lattice-theoretic generalisation of the conflict-driven clause learning algorithm in modern sat solvers to lattice-based abstractions. We use floating-point intervals to reason about the ranges of variables, which allows us to directly handle arithmetic and is more efficient than encoding a formula as a bit-vector as in current floating-point solvers. Interval reasoning alone is incomplete, and we obtain completeness by developing a conflict analysis algorithm that reasons natively about intervals. We have implemented this method in the mathsat5 smt solver and evaluated it on assertion checking problems that bound the values of program variables. Our new technique is faster than a bit-vector encoding approach on 80 % of the benchmarks, and is faster by one order of magnitude or more on 60 % of the benchmarks. The generalisation of cdcl we propose is widely applicable and can be used to derive abstraction-based smt solvers for other theories.
Martin Brain, Vijay Victor D'Silva, Alberto Griggio, Leopold Haller, Daniel Kroening
Formal Methods Syst. Des.2
2013 Abstract conflict driven learning
abstract
Modern satisfiability solvers implement an algorithm, called Conflict Driven Clause Learning, which combines search for a model with analysis of conflicts. We show that this algorithm can be generalised to solve the lattice-theoretic problem of determining if an additive transformer on a Boolean lattice is always bottom. Our generalised procedure combines overapproximations of greatest fixed points with underapproximation of least fixed points to obtain more precise results than computing fixed points in isolation. We generalise implication graphs used in satisfiability solvers to derive underapproximate transformers from overapproximate ones. Our generalisation provides a new method for static analysers that operate over non-distributive lattices to reason about properties that require disjunction.
Vijay Victor D'Silva, Leopold Haller, Daniel Kroening
POPL1
2013 Interpolation-Based Verification of Floating-Point Programs with Abstract CDCL
Martin Brain, Vijay Victor D'Silva, Alberto Griggio, Leopold Haller, Daniel Kroening
SAS2
2013 An Abstract Interpretation of DPLL(T)
Martin Brain, Vijay Victor D'Silva, Leopold Haller, Alberto Griggio, Daniel Kroening
VMCAI2
2013 Abstraction of Syntax
Vijay Victor D'Silva, Daniel Kroening
VMCAI1
2012 Satisfiability Solvers Are Static Analysers
Vijay Victor D'Silva, Leopold Haller, Daniel Kroening
SAS1
2012 Numeric Bounds Analysis with Conflict-Driven Learning
Vijay Victor D'Silva, Leopold Haller, Daniel Kroening, Michael Tautschnig
TACAS1
2010 Interpolant Strength
Vijay Victor D'Silva, Daniel Kroening, Mitra Purandare, Georg Weissenbacher
VMCAI1
2010 A lazy approach to symmetry reduction
abstract
Abstract Symmetry reduction is a technique to counter state explosion for systems with regular structure. It relies on idealistic assumptions about indistinguishable components, which in practice may only be similar. In this article, we present a flexible, lazy approach to symmetry-reducing a structure without any prior knowledge about its global symmetry. Instead of a-priori checking for compliance with symmetry conditions, each encountered state is annotated on the fly with information about how symmetry is violated along the path leading to it. The method naturally favors “very symmetric” systems: more similarity among the components leads to greater compression. A notion of subsumption is used to prune the annotated search space during exploration. Previous solutions to the approximate symmetry reduction problem are restricted to specific types of asymmetry, such as up to bisimilarity, or incur a large overhead, either during preprocessing of the structure or during the verification run. In contrast, the strength of our method is its balance between ease of implementation and algorithmic flexibility. We include analytic and experimental results that witness its efficiency.
Thomas Wahl, Vijay Victor D'Silva
Formal Aspects Comput.2
2009 Fixed points for multi-cycle path detection
abstract
Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay identify multi-cycle paths (MCPs), which allow timing to be relaxed, but ignore the set of reachable states, achieving scalability at the cost of a severe lack of precision. Even simple circuits contain paths affecting timing that can only be detected if the set of reachable states is considered. We examine the theoretical foundations of MCP identification and characterise the MCPs in a circuit by a fixed point equation. The optimal solution to this equation can be computed iteratively and yields the largest set of MCPs in a circuit. Further, we define conservative approximations of this set, show how different MCP identification methods in the literature compare in terms of precision, and show one method to be unsound. The practical application of these results is a new method to detect multi-cycle paths using techniques for computing invariants in a circuit. Our implementation performs well on several benchmarks, including an exponential improvement on circuits analysed in the literature.
Vijay Victor D'Silva, Daniel Kroening
DATE1
2008 Approximation Refinement for Interpolation-Based Model Checking
Vijay Victor D'Silva, Mitra Purandare, Daniel Kroening
VMCAI1
2008 A Survey of Automated Techniques for Formal Software Verification
abstract
The quality and the correctness of software are often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific flaws. This paper surveys algorithms that perform automatic static analysis of software to detect programming errors or prove their absence. The three techniques considered are static analysis with abstract domains, model checking, and bounded model checking. A short tutorial on these techniques is provided, highlighting their differences when applied to practical problems. This paper also surveys tools implementing these techniques and describes their merits and shortcomings.
Vijay Victor D'Silva, Daniel Kroening, Georg Weissenbacher
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1