Write disturbance error (WDE) appears as a serious reliability problem preventing phase-change memory (PCM) from general commercialization, and therefore several studies have been proposed to mitigate WDEs. Verify-and-correction (VnC) eliminates WDEs by always verifying the data correctness on neighbors after programming, but incurs significant performance overhead. Encoding-based schemes mitigate WDEs by reducing the number of WDE-vulnerable data patterns; however, mitigation performance notably fluctuates with applications. Moreover, encoding-based schemes still rely on VnC-based schemes. Cache-based schemes lower WDEs by storing data in a write cache, but it requires several megabytes of SRAM to significantly mitigate WDEs. Despite the efforts of previous studies, these methods incur either significant performance or area overhead. Therefore, a new approach, which does not rely on VnC-based schemes or application data patterns, is highly necessary. Furthermore, the new approach should be transparent to processors (i.e., in-module), because the characteristic of WDEs is determined by manufacturers of PCM products. In this paper, we present an in-module disturbance barrier (IMDB) that mitigates WDEs on demand. IMDB includes a two-level hierarchy comprising two SRAM-based tables, whose entries are managed with a dedicated replacement policy that sufficiently utilizes the characteristics of WDEs. The naive implementation of the replacement policy requires hundreds of read ports on SRAM, which is infeasible in real hardware; hence, an approximate comparator is also designed. We also conduct a rigorous exploration of architecture parameters to obtain a cost-effective design. The proposed method significantly reduces WDEs without noticeable speed degradation or additional energy consumption compared to previous methods.

A rowhammer error represents a loss of data stored in a DRAM cell caused by electromagnetic interference due to repetitive access to the same and/or adjacent rows. Due to the concentrated occurrence of rowhammer errors in specific rows and columns, these errors cannot be corrected by the conventional error correcting code (ECC) commonly used in DRAM devices. Previous techniques avoid these errors by having additional refresh operations that require additional hardware resources and/or power consumption. This paper proposes a different approach to handle rowhammer errors by distributing them across different DRAM rows and columns so that the attack cells are not concentrated on specific rows and columns. To this end, the distribution of rowhammer errors is observed with experiments using several commercial DRAM devices by employing state-of-the-art rowhammer attack techniques. The observation of the rowhammer errors concentrated in specific rows and columns underlies the proposal of an effective DRAM address remapping scheme for re-distribution of rowhammer errors. By using different address mappings to different chips and arrays in a DIMM, the proposed remapping effectively distributes errors over different rows and columns. As a result, the proposed remapping scheme decreases the possibility of multiple errors in a single word, and consequently, reduces uncorrectable errors under single error or single symbol correcting ECC. Experimental results with commercial DIMMs show that the proposed scheme reduces uncorrectable errors by about 95 percent while incurring a small additional hardware cost.

A set-associative cache organization is widely used to achieve a high hit-rate in modern caches, leading to a considerable enhancement in the system performance. In a conventional set-associative cache, tag and data arrays are simultaneously accessed to achieve fast access, but doing so causes a large amount of energy consumption. Previous attempts, such as way prediction and sequential tag access for energy reduction, are still associated with substantial energy consumption due to the tag access. This paper presents a new cache organization termed Segmented Tag Cache (STC), which reduces the amount of energy consumed during the tag access. The proposed organization initially implements a new tag organization that supports partial tag access. More specifically, the tag array is segmented into two parts, and partial tag access only reads low-order part of the tag. A cache access scheme suitable for the proposed tag organization then are developed. Under the scheme, the delay of the tag organization is hidden by the data access delay, avoiding an increase in the overall cache access time to be maintained. Simulation results show that the STC reduces the energy-delay product by approximately 58 percent compared to the conventional cache organizations with a negligible performance penalty.

Phase-change memory (PCM) is a non-volatile memory device with favorable characteristics such as persistence, byte-addressability, and lower latency when compared to flash memory. However, it comprises memory cells that have limited lifetime and higher access latency than DRAM. The row buffer size of a PCM is preferred to be larger than 128B to fill the latency gap between two memories and to reduce the metadata overhead incurred by wear leveling. As the cache line size in a general-purpose processor is 64B, a read-modify-write (RMW) module is required to be placed between the processor and the PCM, which in turn induces a performance degradation. To reduce such an overhead and enhance the reliability of a device, this paper presents a new RMW architecture. The proposed model introduces a DRAM cache in the RMW module, which minimizes redundant read operations for write operations by pre-fetching the entire transaction unit instead of merely caching the 64B requested data. Furthermore, a typeless merge operation is performed with the proposed cache by gathering multiple commands accessing consecutive addresses, irrespective of whether they are READ or WRITE. Simulation results indicate that the proposed method enhances the speed by 3.2 times and the reliability by 49 percent as compared to the baseline model.

Golomb-Rice coding is one of the popular variable-length codings which require quantization of input data to meet the target compression ratio. In order to obtain the optimal quantization level, a conventional iterative approach increases the quantization level one by one until the target ratio is achieved. This iterative approach makes it difficult to implement in hard ware because the number of iterations cannot be estimated at hardware design time. This paper proposes a non-iterative algorithm for Golomb-Rice coding to estimate a near-optimal quantization level. To this end, the algorithm performs Golomb-Rice coding without any quantization of input data and then uses this coding result to estimate the codeword length with quantization. Based on the estimation, a near-optimal quantization level that meets the target length is selected. For the case when the selected level is not optimal, the algorithm performs additional Golomb-Rice codings with modified quantization levels which guarantee the codeword to meet the target length. Experimental results with twenty-four Kodak images show that the proposed coders practically cover all the optimal quantization levels.