Spiking Transformers constitute an emerging class of neural architectures that seek to unify the representational power of Transformer-based models with the computational efficiency of spiking neural networks (SNNs). By leveraging discrete spike-based communication and event-driven processing, Spiking Transformers enable temporally sparse computation while maintaining the global context modeling and scalability inherent to self-attention mechanisms. This integration facilitates energy-efficient sequence modeling and opens new avenues for deploying large-scale attention-based models on neuromorphic hardware. However, existing Spiking Transformer architectures often incur substantial memory overhead, limiting their suitability for deployment in resource-constrained environments such as edge devices. To address this limitation, we propose SpikeViT, an efficient Spiking Transformer architecture designed to minimize memory consumption while preserving representational capacity. The architecture adopts a parallel design, combining a convolutional SNN with a lightweight transformer, connected via bidirectional cross-modal bridges that enable efficient tokenization and integration of spike-based features. Experimental results on the CIFAR10-DVS dataset show that SpikeViT achieves competitive accuracy while reducing memory footprint by up to 50% compared to state-of-the-art models, making it well-suited for deployment in energy- and memory-constrained neuromorphic systems.

Recent advancements in neuroscience research have propelled the development of Spiking Neural Networks (SNNs), which not only have the potential to further advance neuroscience research but also serve as an energy-efficient alternative to Artificial Neural Networks (ANNs) due to their spike-driven characteristics. However, previous studies often overlooked the multiscale information and its spatiotemporal correlation between event data, leading SNN models to approximate each frame of input events as static images. We hypothesize that this oversimplification significantly contributes to the performance gap between SNNs and traditional ANNs. To address this issue, we have designed a Spiking Multiscale Attention (SMA) module that captures multiscale spatiotemporal interaction information. Furthermore, we developed a regularization method named Attention ZoneOut (AZO), which utilizes spatiotemporal attention weights to reduce the model's generalization error through pseudo-ensemble training. Our approach has achieved state-of-the-art results on mainstream neuromorphic datasets. Additionally, we have reached a performance of 77.1\% on the Imagenet-1K dataset using a 104-layer ResNet architecture enhanced with SMA and AZO. This achievement confirms the state-of-the-art performance of SNNs with non-transformer architectures and underscores the effectiveness of our method in bridging the performance gap between SNN models and traditional ANN models.

Large Language Models (LLMs) have demonstrated unprecedented capabilities in language understanding and generation, yet their significant computational requirements pose substantial challenges for scalability and environmental sustainability. In this introductory review, we examine the algorithm-hardware co-design strategies necessary for developing ultra-low-power LLMs. We begin by reviewing model-level approaches– efficient architectures, quantization, sparsity, distillation–that reduce parameter count and memory movement. We discuss hardware-centric innovations, including event-driven neuromor-phic accelerators, near-memory computing paradigms, and spe-cialized number formats, illustrating how these platforms leverage compressed models for substantial gains in energy efficiency. Finally, we address emerging frontiers beyond digital systems that may further reduce power consumption. We offer a blueprint for enabling low-power LLMs, emphasizing the necessity of cross-disciplinary collaboration for efficient AI at scale.

Continual learning (CL) in artificial intelligence enables systems to adapt and accumulate knowledge over time. However, a significant challenge in CL is catastrophic forgetting, where models lose previously learned information when exposed to new data distributions. This study investigates the potential of spiking neural networks (SNNs) and their quantized variants in mitigating catastrophic forgetting. The rationale is that by using sparsely activated neurons, the weight updates are likewise sparse, which may slow the forgetting process. We conduct a comprehensive evaluation of both Quantized SNNs (QSNN) and Post-Quantized SNNs (PQSNNs) under varying quantization levels (8-bit, 4-bit, and 2-bit) across two distinct scenarios: digit recognition with shifting data distributions (MNIST and Permuted MNIST datasets) and complex temporal pattern learning (Spiking Heidelberg Digits dataset). This allows us to assess the models’ resilience under aggressive quantization regimes and diverse learning challenges. Our experimental framework rigorously tests the models for accuracy, loss, and activation sparsity to quantify the extent of catastrophic forgetting. Our findings indicate that PQSNNs 8-bit and 4-bit models are approximately on par with the baseline SNN, in terms of accuracy and test loss while minimizing significant compromise, side-stepping the need for retraining in the quantization-aware regime.

Current open-loop deep brain stimulation (DBS) implants continuously apply electrical current to reduce motor symptoms in patients with Parkinson’s disease (PD). However, neural dynamics are patient-specific, and open-loop DBS systems are energy-inefficient as they can provide ineffective and unnecessary stimulus. Closed-loop DBS systems offer a more efficient and adaptive approach to delivering DBS. Advances in simulating biomarker responses across cortex-basal ganglia-thalamus (CBGT) networks has accelerated closed-loop DBS development. While deep learning shows promise for optimizing closed-loop stimulation, its high computational demands challenge the battery life of implanted DBS devices. Spiking neural networks (SNNs) offer an energy-efficient alternative to traditional neural networks. They benefit from the ability to take advantage of sparse activations of neurons and to transmit information as spikes. We propose a test bench for DBS parameter optimization by introducing a rat model of the CBGT network in a reinforcement learning (RL) environment and train a deep spiking Q network (DSQN) to validate an end-to-end spike model. This marks a step towards the first closed-loop benchmark with end-to-end spiking, from sensory inputs, to the model, to the stimulus outputs.

While deep learning models have seen significant success across various domains, their black-box learning nature and lack of interpretability affect their reliability in safety-critical applications like medical diagnostics and autonomous vehicles. In an attempt to address these limitations, Bayesian neural networks (BNNs) offer a promising alternative by incorporating uncertainty estimation into model predictions, enhancing transparency and decision-making. However, BNN development has primarily focused on efficient, high-fidelity approximate inference and guaranteed convergence in asymptotic settings. These are unsuitable for modern high-dimensional, multi-modal, and non-asymptotic deep learning applications, undermining their theoretical advantages. To bridge this gap, this paper provides in-depth reviews on how approximate Bayesian inference leverages deep learning optimization to achieve high efficiency and fidelity in high-dimensional spaces and multi-modal loss landscapes. It also reconciles Bayesian consistency with generalization objectives in non-asymptotic settings and investigates the generalization capabilities of BNNs. Additionally, this survey examines the often-overlooked expressiveness of BNNs, emphasizing how weight uncertainty and the absence of in-between uncertainty affect their performance. This survey aims to inspire BNN practitioners to adopt a deep learning perspective and offer valuable insights to propel further advancements in the field.

Transformers have achieved superhuman capabilities in language generation. This comes at a significant energy cost, with inference for models like OpenAI’s ChatGPT estimated to run into hundreds of thousands of dollars per day. In stark contrast, the human brain operates with far great energy efficiency. This extended abstract, based on our educational session at Embedded Systems Week, explores the parallels between spiking neural networks (SNNs) and language models, higlighting their similarities with linear recurrent and state-space models. By examining these connections, we explore a pathway toward the development of energy-efficient language models, which may substantially reduce operational costs.

Recent advances in robot-assisted surgery have resulted in progressively more precise, efficient, and minimally invasive procedures, sparking a new era of robotic surgical intervention. This enables doctors, in collaborative interaction with robots, to perform traditional or minimally invasive surgeries with improved outcomes through smaller incisions. Recent efforts are working toward making robotic surgery more autonomous which has the potential to reduce variability of surgical outcomes and reduce complication rates. Deep reinforcement learning methodologies offer scalable solutions for surgical automation, but their effectiveness relies on extensive data acquisition due to the absence of prior knowledge in successfully accomplishing tasks. Due to the intensive nature of simulated data collection, previous works have focused on making existing algorithms more efficient. In this work, we focus on making the simulator more efficient, making training data much more accessible than previously possible. We introduce Surgical Gym, an open-source high performance platform for surgical robot learning where both the physics simulation and reinforcement learning occur directly on the GPU. We demonstrate between 100-5000× faster training times compared with previous surgical learning platforms. The code is available at: https://github.com/SamuelSchmidgall/SurgicalGym.

Auto-encoders are capable of performing input re-construction through an encoder-decoder structure. These net-works can serve many purposes such as noise removal and anomaly detection, whilst being trained without the need for labelled data. Spiking auto-encoders can utilise asynchronous spikes to potentially improve power and simplify the required hardware. In this work, we propose an efficient spiking auto-encoder with novel error-modulated STDP learning. Our auto-encoder uses the Time To First Spike (TTFS) encoding scheme and needs to update all synaptic weights only once per input. Also, it needs only an average of 8 spikes in its hidden layer for reconstruction, leading to a very sparse and hence potentially power-efficient implementation. We demonstrate decent reconstruction ability for MNIST and the challenging Caltech Face/Motorbike datasets and achieve excellent noise removal from MNIST images.

Autonomous driving demands an integrated approach that encompasses perception, prediction, and planning, all while operating under strict energy constraints to enhance scalability and environmental sustainability. We present Spiking Autonomous Driving (SAD), the first unified Spiking Neural Network (SNN) to address the energy challenges faced by autonomous driving systems through its event-driven and energy-efficient nature. SAD is trained end-to-end and consists of three main modules: perception, which processes inputs from multi-view cameras to construct a spatiotemporal bird's eye view; prediction, which utilizes a novel dual-pathway with spiking neurons to forecast future states; and planning, which generates safe trajectories considering predicted occupancy, traffic rules, and ride comfort. Evaluated on the nuScenes dataset, SAD achieves competitive performance in perception, prediction, and planning tasks, while drawing upon the energy efficiency of SNNs. This work highlights the potential of neuromorphic computing to be applied to energy-efficient autonomous driving, a critical step toward sustainable and safety-critical automotive technology. Our code is available at [https://github.com/ridgerchu/SAD](https://github.com/ridgerchu/SAD).

Precise and reliable measurement of wind power uncertainty plays a significant role in the economic operation and real-time control of the smart grid. In this paper, a novel spiking neural network (SNN) architecture is proposed for solving regression tasks, and a multi-objective gradient descent (MOGD) algorithm is employed to generate high-quality wind power prediction intervals (PIs). SNNs improve upon conventional artificial neural networks (ANNs) by encoding interneuron communication into temporally-distributed spikes, which reduce memory access frequency and data communication, and therefore, the computational power requirements of deep learning workloads. This becomes exceedingly important for continual data analysis in remote geographic regions which often lack reliable cloud access and power supply, where many wind power farms are stationed. Given that neuron spikes are all stereotypically treated to be identical, they are a natural fit for tasks that may conflict in a common network architecture, such as multimodal data or where multiple, potentially competing, objectives are being optimized for. This paper proposes an SNN architecture that achieves comparable performance with its ANN counterpart on a complex regression task, i.e., wind power interval prediction. The resulting multi-objective SNN demonstrates superior performance as compared with those from state-of-art ANNs in wind power interval prediction.

This paper presents a spiking neural network (SNN) accelerator made using fully open-source EDA tools, process design kit (PDK), and memory macros synthesized using Open-RAM. The chip is taped out in the 130 nm SkyWater process and integrates over 1 million synaptic weights, and offers a reprogrammable architecture. It operates at a clock speed of 40 MHz, a supply of 1.8 V, uses a PicoRV32 core for control, and occupies an area of 33.3 mm2. The throughput of the accelerator is 48,262 images per second with a wallclock time of 20.72$\mu \mathbf{s}$, at 56.8 GOPS/W. The spiking neurons use hysteresis to provide an adaptive threshold (i.e., a Schmitt trigger) which can reduce state instability. This results in high performing SNNs across a range of benchmarks that remain competitive with state-of-the-art, full precision SNNs. The design is open sourced and available online: https://githuh.com/sJmth/OpenSpike

Single-cell RNA sequencing is an emerging technique in the field of biology that departs radically from the previous assumption of gene-expression homogeneity within a tissue. The large quantity of data generated by this technology enables discoveries of cellular biology and disease mechanics that were previously not possible, and calls for accurate, scalable, and efficient processing pipelines. In this work, we propose SSCAE (spiking single-cell autoencoder), a novel SNN-based autoencoder for sc-RNA-seq dimensionality reduction. We apply this architecture to a variety of datasets, and the results show that it can match and surpass the performance of current state-of-the-art techniques. Moreover, the potential of this technique lies in its ability to be scaled up and to take advantage of neuromorphic hardware, circumventing the memory bottleneck that currently limits the size of sequencing datasets that can be processed.

We present a fully memristive spiking neural network (MSNN) consisting of novel memristive neurons trained using the backpropagation through time (BPTT) learning rule. Gradient descent is applied directly to the memristive integrate-and-fire (MIF) neuron designed using analog SPICE circuit models, which generates distinct depolarization, hyperpolarization, and repolarization voltage waveforms. Synaptic weights are trained by BPTT using the membrane potential of the MIF neuron model and can be processed on memristive crossbars. The natural spiking dynamics of the MIF neuron model are fully differentiable, eliminating the need for gradient approximations that are prevalent in the spiking neural network literature. Despite the added complexity of training directly on SPICE circuit models, we achieve 97.58% accuracy on the MNIST test set and 75.26% on the Fashion-MNIST test set, which is considerably high among all fully MSNNs with small-scale neural networks.

The brain is the perfect place to look for inspiration to develop more efficient neural networks. The inner workings of our synapses and neurons provide a glimpse at what the future of deep learning might look like. This article serves as a tutorial and perspective showing how to apply the lessons learned from several decades of research in deep learning, gradient descent, backpropagation, and neuroscience to biologically plausible spiking neural networks (SNNs). We also explore the delicate interplay between encoding data as spikes and the learning process; the challenges and solutions of applying gradient-based learning to SNNs; the subtle link between temporal backpropagation and spike timing-dependent plasticity; and how deep learning might move toward biologically plausible online learning. Some ideas are well accepted and commonly used among the neuromorphic engineering community, while others are presented or justified for the first time here. A series of companion interactive tutorials complementary to this article using our Python package,snnTorch, are also made available: https://snntorch.readthedocs.io/en/latest/tutorials/index.html.

The impact of device and circuit-level effects in mixed-signal Resistive Random Access Memory (RRAM) accelerators typically manifest as performance degradation of Deep Learning (DL) algorithms, but the degree of impact varies based on algorithmic features. These include network architecture, capacity, weight distribution, and the type of inter-layer connections. Techniques are continuously emerging to efficiently train sparse neural networks, which may have activation sparsity, quantization, and memristive noise. In this paper, we present an extended Design Space Exploration (DSE) methodology to quantify the benefits and limitations of dense and sparse mapping schemes for a variety of network architectures. While sparsity of connectivity promotes less power consumption and is often optimized for extracting localized features, its performance on tiled RRAM arrays may be more susceptible to noise due to under-parameterization, when compared to dense mapping schemes. Moreover, we present a case study quantifying and formalizing the trade-offs of typical non-idealities introduced into l-Transistor-l-Resistor (ITIR) tiled memristive architectures and the size of modular crossbar tiles using the CIFAR-10 dataset.

We present a fully memristive spiking neural network (MSNN) consisting of physically-realizable memristive neurons and memristive synapses to implement an unsupervised Spike Timing Dependent Plasticity (STDP) learning rule. The system is fully memristive in that both neuronal and synaptic dynamics can be realized by using memristors. The neuron is implemented using the SPICE-level memristive integrate-and-fire (MIF) model, which consists of a minimal number of circuit elements necessary to achieve distinct depolarization, hyperpolarization, and repolarization voltage waveforms. The proposed MSNN uniquely implements STDP learning by using cumulative weight changes in memristive synapses from the voltage waveform changes across the synapses, which arise from the presynaptic and postsynaptic spiking voltage signals during the training process. Two types of MSNN architectures are investigated: 1) a biologically plausible memory retrieval system, and 2) a multi-class classification system. Our circuit simulation results verify the MSNN’s unsupervised learning efficacy by replicating biological memory retrieval mechanisms, and achieving 97.5% accuracy in a 4-pattern recognition problem in a large scale discriminative MSNN.

We propose an approximate tensor processing unit (APTPU), which includes two main components: (1) approximate processing elements (APEs) consisting of a low-precision multiplier and an approximate adder, and (2) pre-approximate units (PAUs) which are shared among the APEs in the APTPU’s systolic array, functioning as the steering logic to pre-process the operands and feed them to the APEs. We conduct extensive experiments to evaluate the performance of the APTPU across various configurations and various workloads. The results show that the APTPU’s systolic array achieves up to$5.2\times \textit {TOPS}/mm^{2}$and$4.4\times \textit {TOPS}/W$improvements compared to that of a conventional systolic array design. The comparison between the proposed APTPU and in-house TPU designs shows that we can achieve approximately$2.5\times $and$1.2\times $area and power reduction, respectively, while realizing comparable accuracy. Finally, a comparison with the state-of-the-art approximate systolic arrays shows that the APTPU can realize up to$1.58\times $,$2\times $, and$1.78\times $, reduction in delay, power, and area, respectively, while using similar design specifications and synthesis constraints.

This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfOxmemristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between$5.2\times - 17.3\times $, which also accounts for intermediate voltage buffering to alleviate the memristive loading problem.

The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25–240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1–3 line decoder and a ternary 2–9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed.

Artificial intelligence (AI) and health sensory data-fusion hold the potential to automate many laborious and time-consuming processes in hospitals or ambulatory settings, e.g. home monitoring and telehealth. One such unmet challenge is rapid and accurate epileptic seizure annotation. An accurate and automatic approach can provide an alternative way to label seizures in epilepsy or deliver a substitute for inaccurate patient self-reports. Multimodal sensory fusion is believed to provide an avenue to improve the performance of AI systems in seizure identification. We propose a state-of-the-art performing AI system that combines electroencephalogram (EEG) and electrocardiogram (ECG) for seizure identification, tested on clinical data with early evidence demonstrating generalization across hospitals. The model was trained and validated on the publicly available Temple University Hospital (TUH) dataset. To evaluate performance in a clinical setting, we conducted non-patient-specific pseudo-prospective inference tests on three out-of-distribution datasets, including EPILEPSIAE (30 patients) and the Royal Prince Alfred Hospital (RPAH) in Sydney, Australia (31 neurologists-shortlisted patients and 30 randomly selected). Our multimodal approach improves the area under the receiver operating characteristic curve (AUC-ROC) by an average margin of 6.71% and 14.42% for deep learning techniques using EEG-only and ECG-only, respectively. Our model's state-of-the-art performance and robustness to out-of-distribution datasets show the accuracy and efficiency necessary to improve epilepsy diagnoses. To the best of our knowledge, this is the first pseudo-prospective study of an AI system combining EEG and ECG modalities for automatic seizure annotation achieved with fusion of two deep learning networks.

Volitional control of prostheses is most commonly achieved by myoelectric signalling. The electromyograph (EMG) is detected and processed by a controller, that decodes and relates the signal to the corresponding position of the prosthetic. Myoelectric signalling is limited in users by two factors: lack of nerve endings corresponding to the position of the amputation, and neurological damage resulting in poor signal control. Improved prosthesis control has been demonstrated by the addition of feedback sensors based on computer vision and inertial measurement units. Computer vision requires a significant level of processing, resulting in a high latency and high power usage. In this paper, we propose a means of overcoming this limitation by use of in-vivo retinal signalling to complement EMG for improved control. This is demonstrated using a real-time conductance- based simulator as the sole method of control for an upper-limb prosthesis. Input image streams are received by a camera and used to activate the combined rod and cone photoreceptor cell responses. This in turn generates a spike train which is counted and averaged over time, and passed to an Arduino-based control system which modulates the behavior of the prosthesis. We seek to use this system to lower the experimental barriers of in-vivo ganglion electrical signalling by presenting a way to use retina emulation. A link to the simulator is provided.

Deep neural network inference accelerators are rapidly growing in importance as we turn to massively parallelized processing beyond GPUs and ASICs. The dominant operation in feedforward inference is the multiply-and-accumlate process, where each column in a crossbar generates the current response of a single neuron. As a result, memristor crossbar arrays parallelize inference and image processing tasks very efficiently. In this brief, we present a 3-D active memristor crossbar array 'CrossStack', which adopts stacked pairs of Al/TiO2/TiO2-x/Al devices with common middle electrodes. By designing CMOS-memristor hybrid cells used in the layout of the array, CrossStack can operate in one of two user-configurable modes as a reconfigurable inference engine: 1) expansion mode and 2) deep-net mode. In expansion mode, the resolution of the network is doubled by increasing the number of inputs for a given chip area, reducing IR drop by 22%. In deep-net mode, inference speed per-10-bit convolution is improved by 29% by simultaneously using one TiO2/TiO2-xlayer for read processes, and the other for write processes. We experimentally verify both modes on our 10 × 10 × 2 array.

Dynamic vision sensors are able to operate at high temporal resolutions within resource constrained environments, though at the expense of capturing static content. The sparse nature of event streams enables efficient downstream processing tasks as they are suited for power-efficient spiking neural networks. One of the challenges associated with neuromorphic vision is the lack of interpretability of event streams. While most application use-cases do not intend for the event stream to be visually interpreted by anything other than a classification network, there is a lost opportunity to integrating these sensors in spaces that conventional high-speed CMOS sensors cannot go. For example, biologically invasive sensors such as endoscopes must fit within stringent power budgets, which do not allow MHz-speeds of image integration. While dynamic vision sensing can fill this void, the interpretation challenge remains and will degrade confidence in clinical diagnostics. The use of generative adversarial networks presents a possible solution to overcoming and compensating for a vision chip's poor spatial resolution and lack of interpretability. In this paper, we methodically apply the Pix2Pix network to naturalize the event stream from spike-converted CIFAR-10 and Linnaeus 5 datasets. The quality of the network is benchmarked by performing image classification of naturalized event streams, which converges to within 2.81% of equivalent raw images, and an associated improvement over unprocessed event streams by 13.19% for the CIFAR-10 and Linnaeus 5 datasets.

We present and experimentally validate two minimal compact memristive models for spiking neuronal signal generation using commercially available low-cost components. The first neuron model is called the Memristive Integrate-and-Fire (MIF) model, for neuronal signaling with two voltage levels: the spike-peak, and the rest-potential. The second model MIF2 is also presented, which promotes local adaptation by accounting for a third refractory voltage level during hyperpolarization. We show both compact models are minimal in terms of the number of circuit elements and integration area. Using the MIF and MIF2 models, we postulate the design of a memristive solid-state brain with an estimation of its surface area and power consumption. Analytical projections show that a memristive solid-state brain could be realized within (i) the surface area of the median human brain, 2,400cm2, (ii) the same volume of the median human brain, and (iii) a total power budget of approximately 20 W using a 3.5 nm technology. Distinct from the past decade of memristive neuron literature, our benchmarks are attained using generic commercially available memristors that are reproducible using off-the-shelf components. We expect this work can promote more experimental demonstrations of memristive circuits that do not rely on prohibitively expensive fabrication processes.

This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.

Hardware implementation of functional neuronal circuits has rapidly become more feasible due to increasing reliability of memristor-CMOS integration at a scale necessitated by neuromorphic processes. Most neuromorphic implementations of the memristor treat it as a variable synaptic weight modulated by conductance. The work in this paper enhances biological plausibility of analog vision system circuits by mimicking the nonlinear dynamics of a network of receptive field that resembles those found in the lateral geniculate nucleus. The memristive circuit provides a biologically accurate response where a single cell behaves simultaneously as its own on-center receptive field, and as the off-surround receptive field of adjacent cells. It maximally responds to spatial variations of light. Each output is a fundamental unit of cortical visual information, and we show how the receptive field of each neuron can be superimposed to perceive edges and recognize objects when scaled to higher cortical areas. The functionality of the array is verified in SPICE simulations.

Human cognition, perception, and memory are partially attributed to the synchronicity of neuronal dynamics in the prefrontal cortex, and growing evidence indicates that age-related decline in working memory is causally linked to dissonance in neuronal firing patterns. Neuromodulation of spike timing has been classically considered an invasive process, met with resistance due to technological and ethical constraints. Thus, non-invasive neurostimulation techniques have been used to treat and manage a diverse range of health conditions, and more recently it has been suggested to enhance human cognition and working memory. In this paper, we propose a low-cost transcranial alternating current neurostimulator wearable targeting frequencies in the theta wave band (4-8 Hz), which are crucial for the functioning of normal memory and attention. Prior work on transcranial stimulation indicates that modulating large-scale neural activity is achievable through both entrainment and resonance effects, by recruiting a larger population of neurons into task-relevant rhythmic firing networks. We conduct a simulation current density within the brain in response to the wearable, using SimNIBS, followed by experimental results of our board-level implementation with a test study of various electrodes, by connecting them to an impedance of 20 kΩ.

Existing computational models of the retina often compromise between the biophysical accuracy and a hardware-adaptable methodology of implementation. When compared to the current modes of vision restoration, algorithmic models often contain a greater correlation between stimuli and the affected neural network, but lack physical hardware practicality. Thus, if the present processing methods are adapted to complement very-large-scale circuit design techniques, it is anticipated that it will engender a more feasible approach to the physical construction of the artificial retina. The computational model presented in this research serves to provide a fast and accurate predictive model of the retina, a deeper understanding of neural responses to visual stimulation, and an architecture that can realistically be transformed into a hardware device. Traditionally, implicit (or semi-implicit) ordinary differential equations (OES) have been used for optimal speed and accuracy. We present a novel approach that requires the effective integration of different dynamical time scales within a unified framework of neural responses, where the rod, cone, amacrine, bipolar, and ganglion cells correspond to the implemented pathways. Furthermore, we show that adopting numerical integration can both accelerate retinal pathway simulations by more than 50% when compared with traditional ODE solvers in some cases, and prove to be a more realizable solution for the hardware implementation of predictive retinal models.

The development of a bioinspired image sensor, which can match the functionality of the vertebrate retina, has provided new opportunities for vision systems and processing through the realization of new architectures. Research in both retinal cellular systems and nanodriven memristive technology has made a challenging arena more accessible to emulate features of the retina that are closer to biological systems. This paper synthesizes the signal flow path of photocurrent throughout a retina in a scalable 180-nm CMOS technology, which initiates at a 128 × 128 active pixel image sensor, and converges to a 16 × 16 array, where each node emits a spike train synonymous to the function of the retinal ganglionic output cell. This signal can be sent to the visual cortex for image interpretation as part of an artificial vision system. Layers of memristive networks are used to emulate the functions of horizontal and amacrine cells in the retina, which average and converge signals. The resulting image matches biologically verified results within an error margin of 6% and exhibits the following features of the retina: lateral inhibition, asynchronous adaptation, and a low-dynamic-range integration active pixel sensor to perceive a high-dynamic-range scene.

This paper explores the dynamic behavior of dual flux coupled memristor circuits in order to further ascertain fundamental theory of memristor circuits. Different cases of flux coupling are mathematically modelled where two memristors are connected in both series and parallel, with consideration given to the polarity of each device. The dynamic behavior is characterized based on the constitutive relations, with a variation of memductance represented in terms of flux, charge, voltage and current. The agreement between theoretical and simulation analyses affirm the memristor closure theorem with coupled memristor circuits behaving as a different type of memristor with higher complexity.

This paper presents a CMOS image sensor (CIS) VLSI architecture based on a single-inverter time-to-threshold pulsewidth modulation circuitry capable of operating as low as 330-mV supply voltage while retaining a signal-to-noise ratio of 24 dB; an important characteristic being demanded by very low voltage portable CIS-based equipment such as disposable medical cameras and on-chip autonomous wireless security vision systems. A 64 × 64 pixel array was fabricated using standard 130-nm CMOS process consuming only 5.9 nW/pixel with integration time of 2 ms at +0.5 V supply. The high fill factor of 58% facilitated a better SNR at a low supply voltage when compared with other CIS architectures. The pixel has a dynamic range of 54 dB with 7.8 frame per second.

This live demonstration presents a high fill factor 6 transistor per pixel CMOS image sensor (CIS) based on a single inverter that modulates light illumination to pulse width supporting ultra low supply voltage requirements. It has a compact readout circuitry for pulse-based signal processing without A/D converter at the output. A 64 × 64 pixel array was fabricated using 130 nm CMOS technology. The chip operated under a +VDDas low as 500 mV with power consumption of only 27 nW per pixel. The fill factor is 58%, which is significantly larger than those conventional CMOS imagers.

The nonvolatile memory property of a memristor enables the realization of new methods for a variety of computational engines ranging from innovative memristive-based neuromorphic circuitry through to advanced memory applications. The nanometer-scale feature of the device creates a new opportunity for realization of innovative circuits that in some cases are not possible or have inefficient realization in the present and established design domain. The nature of the boundary, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces challenges in modeling, characterization, and simulation of future circuits and systems. Here, a deeper insight is gained in understanding the device operation, leading to the development of practical models that can be implemented in current computer-aided design (CAD) tools.

Large-capacity content addressable memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore's Law for a few more years. This paper provides a new approach towards the design and modeling of Memory resistor (Memristor)-based CAM (MCAM) using a combination of memristor MOS devices to form the core of a memory/compare logic cell that forms the building block of the CAM architecture. The non-volatile characteristic and the nanoscale geometry together with compatibility of the memristor with CMOS processing technology increases the packing density, provides for new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power dissipation, and has scope for speed improvement as the technology matures.

Although silicon technology is continuously evolving to produce smaller systems with minimized power dissipation and at a lower cost and improved reliability, it is expected that this trend will have matured between 2014 and 2016. This will eventually lead to the integration of a multiplicity of technologies rather than simply silicon technology. This multiplicity of technologies will be the driving force to create unprecedented opportunities for realization of new integrated systems. The marriage of microelectronics and photon-based sciences with that of nanochemistry and biotechnology brings into the forefront the evolutionary progress in future SoC technology leading to intelligent systems-on-chip ( iSoCs) as the frontier of innovative products. iSoCs will enable the development of novel circuits and systems with extraordinary new properties relevant to nearly every sector of the economy. This integration, supported by a bio-based technology, provides the foundation for a future in which sensing, imaging, information processing, and communication can be integrated. New generations of auto-sensor health monitoring devices based on intelligent diagnostics such as intelligent pacemakers that respond to individual's activity needs, wearable sensors and smart communicators, etc., become part of an important "toolkit" to serve our aging population, leading to the emerging concept of iSoC as its fundamental building block. This evolutionary change is the result of revolutionary concepts that link microelectronics, photonics, nanochemistry, and biotechnology,-a crucial platform-bringing into the forefront the significance of iSoC technology as the future frontier of innovative research and related products.

In this paper, we present a dataflow-oriented architecture for a modified SPIHT algorithm which is suitable for VLSI implementation. The input into the architecture is a bit stream of the wavelet coefficients in the depth-first search (DFS) format and the output from the architecture is a data stream containing the significance map (MAP) and successive-approximation quantization (SAQ) symbols for the SPIHT algorithm. The memory requirements for the architecture are reduced by transmitting the MAP and SAQ symbols as they are generated. The MAP and SAQ symbols are formulated in view of the DFS coefficient bit stream and the corresponding VLSI architecture to implement the formulated requirements is presented. Simulations are also presented to compare the coding efficiency for the modified SPIHT architecture versus the complete SPIHT algorithm.

In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 /spl mu/m CMOS technology.

Constrained via minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.

This paper presents a survey of low-power digital Gallium Arsenide logic applicable to high performance VLSI circuits and systems and proposes new design concepts in methodology and architecture based on the implementation of Pseudo-Dynamic Latched Logic in order to achieve reasonable power-delay-area tradeoff. The approach is highly suitable for self-timed systems where the complexities of clock skew are avoided and power saving is achieved through pipelined architectures. The emergence of low-power Complementary HIGFET (C-HICFET) technology enables the realisation of new high performance low-power architectures. The viability of nu-GaAs (/spl nu/GaAs) as applied to C-HIGFET is discussed and the concept of 'soft' hardware referred as 'flexware' is introduced as a new design paradigm for GaAs.

A novel smart pixel opto-VLSI architecture to implement a complete 2-D wavelet transform of real-time captured images is presented. The smart pixel architecture enables the realisation of a highly parallel, compact, low power device capable of real-time capture, compression, decompression and display of images suitable for mobile multimedia communication applications.

The parameter search technique allows us to approximate a high-order model by a much lower order autoregressive moving average (ARMA) model with a performance that is nearly indistinguishable from the original. Parameter estimation for a system or its model can be achieved through iterative techniques. The problem is considered as one of minimising an error function. The error is defined as the difference between the expected value and the actual value obtained from an initial approximate model. Through iteration the model parameters are refined. Such a recursive parameter estimator (RPE) can be used to greatly reduce the order of certain digital filters with little distortion to their frequency and phase responses. Since digital filters are commonly used in electronic communications and signal processing applications, RPE may be a tool of considerable practical use. To demonstrate this potential, RPE is applied to an FIR model, showing that its order may be reduced considerably with little change to the accuracy of the model.

We introduce a tabular method to perform the last two of the four phases of Martin's compilation process for asynchronous circuit design. The method is then demonstrated with three examples, illustrating that our systematic method is very straight forward, flexible, and convenient to apply, and, hence, it lends itself to automatic compilation.

Although speed independent VLSI circuit design is supported by rich theory at higher levels, it suffers from the lack of an area efficient robust transistor level implementation technique. In this paper we introduce safe cells based on which well-formed STGs can be implemented free of (delay) hazards with no unrealistic assumptions about physical gates. Although this technique still compromises chip area for the sake of preventing hazards, we show that it may achieve a significant area gain in comparison with the two-phase RS-implementation method, which is one of the few true speed independent implementation techniques that we are aware of so far. Delay hazards are then analysed in complex gate based speed independent circuits and hence theorems are developed to identify a subclass of delay hazards.

This paper presents a GaAs IEEE floating point standard single precision multiplier. A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. The combination of the fast arithmetic architecture and compact layout style achieves 4 ns multiplication time with 3.5 W power dissipation at 75/spl deg/C giving 14 mW/MHz. The area is 2.43 mm by 3.77 mm (excluding pads) and uses 28,000 transistors to give a density of 3056 transistors/mm/sup 2/ for 0.8-/spl mu/m GaAs technology.>

Fully autonomous mobile robots often rely on an array of sensors to provide them with an adequate picture of their environment. Furthermore, these systems tend to have strict limitations in terms of available processing capability. Hence the so-called "smart sensing" approach is particularly appropriate as it combines a small size with a reduced requirement for interpretation of sensory input. This paper describes how a visual micro-sensor implemented in VLSI can be used for obstacle avoidance as well as localised path planning or navigation.>