Physical Unclonable Functions (PUFs) are a very useful resource in cryptography with many applications ranging from system authentication to secret key generation. Side-channel attacks (SCAs) are a major concern in any physical implementation of a cryptographic module, and PUFs are no exception. Electromagnetic (EM) leakage from the implementation of a ring-oscillator-based PUF (RO-PUF) can be exploited to retrieve sensitive information that compromises the security of the cryptographic scheme incorporating the PUF. In this paper, we analyse the EM leakage of an RO-PUF implemented on FPGA, highlight its main vulnerabilities, and propose alternative countermeasures and architectures to mitigate the threat of this type of attack. Furthermore, we evaluate the cost in terms of area overhead of the proposed implementations compared to the original design.

The development of hardware countermeasures against hardware attacks has attracted the attention of the scientific community over the past two decades. Side-Channel Analysis (SCA) and Fault Injection Attacks (FIA) represent a significant risk to the security of cryptographic circuits. Combined countermeasures against these types of attack must be carefully designed if both protections are required in the same implementation without interfering with the other. In this paper, a combined proposal is presented to counteract the SCA and FIA attacks. SCA countermeasures are based on a low-entropy masking scheme, while the FIA countermeasure is based on a signature generator detection scheme. Both have been experimentally implemented in an AES cipher in FPGA. Experimental FIA attacks, first-order Correlation Power Analysis (CPA) attacks, and Test Vector Leakage Assessment (TVLA) tests have been carried out to evaluate the improvement in the security levels. The experimental results show that for an increase in area 28.77% and a frequency degradation of 4.05% with respect to the unprotected implementation, the protected Advanced Encryption Standard (AES) scheme shows great security metrics against FIA (99.87% fault coverage) and SCA attacks.

Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting vulnerabilities into the block ciphers currently used in a multitude of applications. In order to minimize this type of vulnerabilities, several mechanisms have been proposed to detect this type of attacks. However, these mechanisms can have a significant cost or not adequately cover the implementations against fault attacks. In this paper a novel approach is proposed, consisting in generating the signatures of the internal state using a Hamming code. This allows to cover a larger amount of faults allowing to detect even or odd bit changes, as well as multi-bit and multi-byte changes, the ones that make ciphers more vulnerable to DFA attacks. As case of study, this approach has been applied to the Advanced Encryption Standard (AES) block cipher implemented on FPGA using T-boxes. The results suggest a higher fault coverage with an overhead of 16% of resource consumption and without any penalty in the frequency degradation.

Today, the large amount of information exchanged among various devices as well as the growth of the Internet of Things (IoT) demand the development of devices that ensure secure communications, preventing malicious agents from tapping sensitive data. Indeed, information security is one of the key challenges to address within the IoT field. Due to the strong resource constraints in some IoT applications, cryptographic algorithms affording lightweight implementations have been proposed. They constitute the so-called lightweight cryptography. A prominent example is the Trivium stream cipher, one of the finalists of the eSTREAM project. Although cryptographic algorithms are certainly simpler, one of their most critical vulnerability sources in terms of hardware implementations is side channel attacks. In this paper, it is studied the vulnerability of field-programmable gate array (FPGA) implementations of Trivium stream ciphers against fault attacks. The design and implementation of a system that alters the clock signal and checks the outcome is also described. A comparison between real and simulated fault injections is carried out in order to examine their veracity. The vulnerability of different versions of the Trivium cipher and their routing dependences has been tested in two different FPGA families. The results show that all versions of the Trivium cipher are vulnerable to fault attacks, although some versions are more vulnerable than others.

This article presents the development of an experimental system to introduce faults in Trivium stream ciphers implemented on FPGA. The developed system has made possible to analyze the vulnerability of these implementations against fault attacks. The developed system consists of a mechanism that injects small pulses in the clock signal, and elements that analyze if a fault has been introduced, the number of faults introduced and its position in the inner state. The results obtained demonstrate the vulnerability of these implementations against fault attacks. As far as we know, this is the first time that experimental results of fault attack over Trivium are presented.