A compact low-noise digital pixel with 15-bit pixel-level two-step analog-to-digital converter (ADC) is presented in this paper. The coarse quantization adopts a 10-bit pulse frequency modulation conversion with a proposed threephase charge-reset circuit. The charge-reset circuit reduces the reset noise charge which is the major noise of this pixel. The fine quantization is implemented by a 5-bit single-slope ADC. It reuses most of the coarse quantization circuit to realize high precision quantization in compact pixel. A 640×512 readout integrated circuit for infrared focal plane array with the 15μm pitch digital pixel is designed in the 0.18 μm1P5M CMOS process for verification. Post-layout simulation results of the digital pixel show that the RMS noise at maximum signal is 0.51LSB, and the integral nonlinearity is +2.3LSB/-3.0LSB. The power consumption per pixel is only 57. 2nW at 120fps.

This paper presents an uncooled infrared imager with flicker noise reduction, which is realized by the proposed phase difference modulation (PDM) method. The PDM method makes noise transfer function (NTF) generate a series of notches to reduce flicker noise. To realize PDM, a high-speed sub-frame readout circuit is proposed. The readout circuit has been manufactured and the output data is processed with FPGA. The measurement results show that the flicker noise power in the frequency range above 10Hz is reduced by 42% compared with traditional method at 60fps full image output rate, and the noise equivalent temperature difference (NETD) is reduced from 40mK to 34mK.

This paper presents a low-power readout circuit with 14-bit column-level extended-counting ADC for 17μm-pitch 1024 × 768 silicon diode uncooled infrared imagers. The ADC's coarse conversion adopts a current-mode DAC to feedback charge into a CTIA-based integrator during integration and the fine conversion is implemented by a SAR ADC after integration. A current self-compensator and a modified DAC are proposed to reduce more than 50% power of the overall integrator compared with conventional structure. The 1024 × 768 readout circuit has been fabricated in the 0.18 μm 1P5M CMOS process. Power consumption of the readout circuit is 104mW and each column ADC only consumes 15μW. Simulation results show that the RMS noise of the readout circuit is 0.9LSB and nonlinearity is 0.06% at 30fps.

This paper presents a new low-power readout structure for 1024×6 infrared focal plane array with 1/2 sub-scan time-delay-integration (TDI) and delay-locked-loop-based (DLL-based) analog-to-digital (A/D) function. The circuit is of low power for its passive sampling, delay, and summation completed by capacitor array. Multiple-capacitor structure is also used to make the circuit suffer less from capacitor mismatch. 1/2 sub-scan function and the distribution of detector array contribute to higher resolution in the direction both along the track and across the track. And the TDI function is combined with A/D process in terms of circuit structure and timing sequence, reducing the noise and enhancing the frame rate. The 14-bit ADC is divided into coarse quantization part and fine quantization part. The former is a conventional 11-bit single-ramp ADC and the latter is realized by 8-phase clocks generated by DLL. This circuit also supports bidirectional scanning and two types of detectors whose photo-current flows into or out of the readout circuit.