Emerging non-volatile memory (NVM) device technologies are advancing in-memory computing (IMC) applications by providing faster computation speeds and reducing resource overhead. Crossbar structures are commonly used in IMC with NVM devices such as memristors to perform matrix-vector multiplication for deep learning and security primitive applications. Large crossbars are required to implement today's deep learning models, especially for implementing specialized Binarized Neural Networks (BNNs) architectures and to construct security primitives such as physical unclonable functions (PUFs). To digitize crossbar currents, current-sense comparators based on current mirrors are widely used in BNN crossbars. However, conventional comparators have a limited current range due to the decrease of the bit-line voltage as the number of active crossbar elements connected to the bit-line increases. This paper presents a current comparator that employs a regulated cascode sensing stage which boosts the input current range by stabilizing the bit-line voltages. By increasing the current range, a larger crossbar size can be supported. Extensive simulations were carried out to verify the proposed technique, demonstrating that a significantly larger crossbar size can be achieved with the proposed comparator compared to a traditional current-sense comparator for the same area and resolution. Designed in a 180 nm technology, the proposed comparator achieves a resolution of 50nA and 100μA for PUF and BNN applications, respectively, and dissipates 198 μW,

This article presents a timing-skew-free time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC). By implementing an architecture with a single sample-and-hold (S/H) network, this design eliminates the need for a costly timing-skew calibration. Additionally, compared to architectures that utilize multiple S/H networks, it offers hardware and power savings. As a result, the proposed design is efficient in terms of energy and area, making it suitable for applications that require multiple ADC channels. A prototype ADC is designed and fabricated in a 28-nm CMOS process. The TI SAR ADC, running at 1.4 GS/s, achieves a signal-to-noise-and-distortion ratio (SNDR) and spurious free dynamic range (SFDR) of 48.1 and 58.4 dB with a Nyquist input, respectively. It dissipates 24 mW, leading to a Walden figure-of-merit (FoM) of 82.4 fJ/conv.-step. The chip occupies an active area of 0.06 mm2.

This article presents a circuit technique to improve the power efficiency of the well-established active-RC continuous-time (CT) Delta-Sigma modulator (DSM). The technique is to add a large capacitor at the virtual ground node of the first amplifier in an active-RC DSM. Without attenuating the in-band signal, this capacitor smooths out the fast transitions in the feedback and suppresses most of the quantization noise before processing by the first amplifier. The transconductance and output swing requirements of the crucial first amplifier can therefore be significantly relaxed. In addition, the technique converts an undesired parasitic pole into a desired one of the loop filter, reducing an amplifier and eliminating the problems associated with the parasitic pole. Last, the large capacitor at the virtual ground node opens a way to reduce the flicker noise because it allows the first amplifier to use large-sized input transistors without performance penalties. To verify the technique, a 3rdorder 1-bit active-RC DSM is designed and fabricated in 180-nm CMOS technology. Clocked at 320 MHz, it achieves a measured signal-to-noise-plus-distortion ratio of 78.7 dB over a 2 MHz bandwidth and a spurious-free dynamic range of 88.4 dB while consuming 0.59 mW, of which the first amplifier takes only 13.5%. The recorded Warden's and Schreier's figure of merits are 20.1 fJ/conv-step and 174 dB respectively. The proposed simple circuit technique makes this otherwise ordinary active-RC modulator one of the most power-efficient CT DSMs.

A highly linear multi-level switched-capacitor (SC) digital-to-analog converter (DAC) is proposed for continuous-time delta-sigma modulators (CTDSMs). A Gm-C CTDSM with a passive frontend low-pass filter (LPF) is further proposed to mitigate the problems of increased settling requirements and worsened anti-aliasing capability (consequences of an SC DAC) so as to realize an extremely power-efficient CTDSM. A 100-kHz bandwidth 40× oversampling 3rd-order CTDSM prototype employing the proposed DAC and modulator topology is fabricated in a low-leakage 65-nm CMOS technology. Experimental results show that the modulator achieves a spurious-free dynamic range (SFDR), dynamic range (DR) and signal-to-noise and distortion ratio (SNDR) of 86.6 dB, 85.1 dB and 78.8 dB, respectively. To the best of our knowledge, this is the first silicon-proven CTDSM with a more-than-3-level DAC that leads to an excellent SFDR while not requiring dynamic element matching, component calibration, precise reference voltages, or an operating frequency higher than the modulator's sampling frequency. The prototype consumes 22.8 μW from a 1.2-V supply, amounting to a Walden's and Schreier's figure of merit (FoM) of 16 fJ/conv.-step and 181.5 dB, respectively, which is the best among state-of-the-art CTDSMs. It further achieves high alias rejections of 52 dB and 58 dB at twice and thrice of the sampling frequency, respectively, and can tolerate a clock period jitter of 3 ns.

Recent progress in continuous-time (CT) Delta-Sigma modulators (DSMs) research has shown that applying a passive RC low-pass filter (LPF) in the feedback path can significantly improve the power efficiency of a CT DSM. On the other hand, to achieve high performance, a CT DSM faces the adverse effects of clock jitter, intersymbol interference (ISI), or degradation of antialiasing ability. These challenges are extremely difficult to tackle simultaneously without consuming excessive power. This paper proposes a Gm-C DSM with a combined RC and switched-capacitor LPF frontend stage to achieve a high performance against aliasing, clock jitter, and ISI simultaneously while having an extremely low power consumption. Transistor-level simulations on an audio band modulator and a 10-MHz bandwidth modulator are given, verifying the high immunity of the proposed circuit to clock jitter, ISI, and aliasing while attaining a power efficiency up to 7.4 fJ/conversion step.

This paper presents an on-chip technique for calibrating static and dynamic DAC errors in a multibit continuous-time (CT) Delta-Sigma (ΔΣ) modulator. Dynamic errors such as inter-symbol-interference (ISI) affect the DAC output at every data transition and significantly deteriorate the in-band noise floor in high-speed applications. In the proposed technique, a compensation current is injected in the loop at every up-transition of input data to cancel the ISI error of each unit cell, thus improving its dynamic linearity. High linearity merged-input-feedback Gm-C integrators have been shown to enhance the converter's linearity and reduce power but require that the feedback DAC common mode matches the input-signal common mode. A biasing circuit for the current-steering feedback DAC is proposed to match its output common mode to the input signal common mode across PVT. Simulation results for a 70 MHz bandwidth, 3rdorder modulator, operating at a 2.8 GHz sampling rate, show a 2.8dB improvement in the in-band noise with the proposed dynamic calibration technique as well as maintaining the common-mode matching requirements across PVT.

A technique to ease the linearity requirement of the input transconductor (Gm) of a Gm-C based continuous-time (CT) Delta-Sigma (ΔΣ) modulator is presented. Compared with RC-based CT ΔΣ modulators, Gm-C-based modulators consume lower power, however they have poorer SNDR due to smaller linear input range. The proposed technique utilizes a single bit quantiser, a 14-tap FIR filter and a compensating Gm cell in the feedback path to cancel the input Gm cell's nonlinearity. System level simulations of a 3rd order modulator demonstrate an improvement of over 30 dB in SFDR with no penalty on the in-band noise floor.

This paper presents a successive-approximation-register (SAR) analogue-to-digital converter (ADC) using a tri-level switching scheme named as reverse VCM-based scheme which maintains good linearity without any driving and accuracy requirements on VCM. A 10-bit SAR ADC is designed in a 0.18 CMOS technology. With a unit capacitor size of 17.2 fF, the ADC consumes 41.9 μW from a 1.8 V voltage supply. The measured signal-to-noise-plus-distortion ratio (SNDR) is 59.6 dB at 2 MS/s. The figure-of-merit (FOM) is 26.9 fJ/conv.-step.