Two critical aspects in IoT are security and resource consumption. Physically Unclonable Functions (PUFs) are hardware security primitives that exploit the inherent manufacturing variations of integrated circuits to generate unique identifiers. Due to their uniqueness and resistance to cloning, they are widely used for IoT device authentication. In this work, a novel approach to enhance the identifiability of compensated measurement PUFs is introduced. This method involves applying specific weight masks to the parameters extracted from the PUF entropy source before conducting comparisons to determine the output bit. This technique has been tested on several types of PUFs constructed using public datasets. As a result, it has been observed that the Equal Error Rate ( EER ) can be greatly improved, up to two orders of magnitude. The main advantage of this technique is that it does not modify the architecture of the compensated measurement PUF (which is interesting for IoT devices, as it does not require extra resources), while it also has proven to be generalizable, i.e., the optimal mask parameters can be found using a small set of devices and, then, generalized to a different bigger set of devices. This way, this proposal contributes to the development of novel authentication schemes for IoT devices, addressing both security and resource efficiency, critical issues in IoT environments. • A novel optimization technique to improve the identifiability of a compensated measurement PUF and its theoretical justification. • The optimization requires only a small subset of devices as a training dataset, enabling generalization to a larger population of devices. • The implementation of this technique and test using different types of PUFs constructed using public databases. • The implementation of one technique which does not require additional hardware resources based on initializing counters to a certain value.

In this work, we propose a novel strategy to increase the identifiability of any PUF that uses the compensated measuring technique. The proposed strategy consists of applying certain Nonlinear Transformations before performing the comparisons of the parameters extracted from the entropy source to obtain the output bit. With this purpose, we apply this technique to different types of PUFs constructed using public datasets, as well as a PUF implemented by ourselves. The results obtained show a significant improvement in the Inter-HD of the PUF of up to 6 percentage points. Likewise, we also show that for some cases, it is possible to improve identifiability by up to two orders of magnitude.

In this work, a novel Weak Physically Unclonable Function (PUF) suitable for FPGA based on 11-LUT Generalized Galois Ring Oscillators (GenGAROs) has been proposed. The GenGARO-PUF has been implemented in 40 Artix-7 FPGAs and 128-bit sequences have been generated for each device. The proposed PUF presents an average Inter-HD of 49.89 %, an average Intra-HD of 1.68 % and an Equal Error Rate (EER) of 2.71 · 10-15. Our proposal has been compared to other state-of-the-art PUFs as well as with a conventional Ring Oscillator PUF (RO-PUF) implemented in the exact same locations of the FPGA. This analysis shows that the proposed PUF can outperform previously proposed PUFs in terms of EER. Finally, an alternative architecture of the proposal using 3-LUT GenGAROs has been implemented and analyzed, proving that it is possible to maintain a high identifiability (EER=6.43 · 10-14) using considerably fewer resources of the FPGA.

Physically unclonable functions (PUFs) have become an important area of study in the field of hardware security. In this paper we have designed a ring oscillator PUF (RO-PUF) implemented it in FPGA and characterised it using a new concept: second-order compensated measurement by two-bit extraction. The results show that it is possible to use two quality bits to generate the response, thus improving the performance compared to conventional RO-PUFs.

In some encryption systems it is necessary to preserve the format and length of the encrypted data. This kind of encryption is called FPE (Format Preserving Encryption) or DPE (Datatype Preserving Encryption). For example, in the case of PCS (Physical Coding Sublayer) at Gigabit Ethernet optical communications, the 8b10b symbol flow can be encrypted at line rate thanks to a symmetric encryption scheme that must preserve the format and coding properties of 8b10b symbols. In this case, since a high speed data flow needs to be encrypted preserving its format, the usage of an FPE stream cipher could be advantageous. For this purpose, a new keystream generator scheme is proposed in this work. It is based on a secure block cipher working in CTR (Counter) mode whose output is subjected to a modulo operation. Moreover, a security analysis for this mode is carried out, deriving an expression for the IND-CPA (Indistinguishability under Chosen Plaintext Attack) advantage of any adversary, concluding that this mode can be considered secure in the same way as traditional modes are. Furthermore, the proposed structure has been implemented over an FPGA (Field Programmable Gate Array) device and adapted to a Gigabit Ethernet application.

We investigate and compare three low complexity circuit topologies to be implemented in programmable logic devices, for the design of True Random Bit Generators for Lightweight Cryptography. The architectures, based on the general idea of Digital Nonlinear Oscillators (DNOs), have been compared on the basis of measurement campaigns, carried out referring to figures of merit specifically introduced to assess the quality and reliability of the oscillators under test.

In this work a new self-synchronized encryption method for 10 Gigabit optical links is proposed and developed. Necessary modifications to introduce this kind of encryption in physical layers based on 64b/66b encoding, such as 10 GBase-R, have been considered. The proposed scheme encrypts directly the 64b/66b blocks by using a symmetric stream cipher based on an FPE (Format Preserving Encryption) block cipher operating in PSCFB (Pipelined Statistical Cipher Feedback) mode. One of the main novelties in this paper is the security analysis done for this mode. For the first time, an expression for the IND-CPA (Indistinguishability under Chosen-Plaintext Attack) advantage of any adversary over this scheme has been derived. Moreover, it has been concluded that this mode can be considered secure in the same way of traditional modes are. In addition, the overall system has been simulated and implemented in an FPGA (Field Programmable Gate Array). An encrypted optical link has been tested with Ethernet data frames, concluding that it is possible to cipher traffic at this level, getting maximum throughput and hiding traffic pattern from passive eavesdroppers.

In this brief we outline a novel perspective for the design of True Random Number Generators in Programmable Logic Devices (PLDs), proposing to bring together PLD design, circuit modeling and the analysis of nonlinear dynamical systems. Although the discussion and experimental results provided in this work refer to FPGA design, the reasoning and concepts have general validity, being easily adaptable to other kind of PLDs, e.g., Complex PLDs (CPLDs). We introduce a novel class of systems, that have been generically named Digital Nonlinear Oscillators, exhibiting complex periodic dynamical behavior, proposing topologies based on Ring Oscillators embedded in looped structures using digital delay blocks and XOR gates. We compared the proposed systems with other solutions proposed in literature, discussing the circuit operation and its nonlinear dynamical behavior.

A new technique for improving the security of a chaotic cryptosystem has been proposed. An encryption system based on a Skew Tent Map using this technique has been implemented on a Virtex 7 FPGA. The results show that, using this method, the randomness of the sequences can be considerably improved by using a small number of extra resources.

In this work a new physical layer encryption method for Ethernet 1000Base-X standard is proposed. The proposed encryption scheme uses a chaotic stream cipher to encrypt the 8b10b symbols flow at PCS (Physical Coding Sublayer) level. The complete system has been implemented in an FPGA (Field Programmable Gate Array). Experimental results are analyzed, concluding that it is possible to cipher traffic at this level and hide the complete Ethernet traffic pattern from any malicious observer. Moreover, no overhead is introduced during encryption and no throughput losses are produced.

In this paper we propose a fast and secure encryption system with a mixed-architecture based on a Modified Logistic Map and a Linear Feedback Shift Register. The system has been simulated showing that it can encrypt and decrypt images efficiently. The encrypted messages have been able to pass the NIST as well as the diehard battery of tests proving that the system is secure.