We report on the development of a time-domain numerical modeling framework to estimate timing jitter in High-Speed Serial Interfaces (HSSI) including a wide range of effects such as Inter-Symbol Interference (ISI) due to channel dispersion, phase noise of transmitter (TX) and receiver (RX) frequency synthesizers and use of bang-bang phase detector in the Clock and Data Recovery (CDR) loop. Based on the step response of the channel, the numerical model computes the response of the system to a random sequence of bits and provides information in terms of eye diagram, bathtub plot and jitter histogram. Different definitions of jitter are investigated, and for each of them we consider the physical effects that are included, eventually identifying that the most complete definition is based on the time distance between the edges instants defined by the CDR and the crossing points of the sampled signal. We also found that this definition is consistent with the features of the bathtub plot. A channel compliant with the PCIe 4.0 standard is used as test vehicle, including the main equalization strategies. The numerical model is then compared to a simple analytical model for the CDR jitter that can be augmented by including Data-Dependent Jitter (DDJ). An approach to system-level analysis based on proper combination of the above elements is eventually proposed to provide quick although accurate aid to the design of CDRs in HSSIs.

This article proposes compact expressions for the jitter in clock and data recovery (CDR) circuits based on bang-bang phase detector including the phase noise of the transmitter and receiver oscillators as well as the quantization noise associated with the finite number of phases of the phase interpolator (PI) that align the receiver clock to the incoming data. Different approaches to perform the Early/Late detection on deserialized data and edge samples are compared: the use of majority voting degrades the CDR bandwidth, increasing the impact of the clock jitter on the CDR jitter; on the other hand, counting the single Early/Late occurrences does not degrade the bandwidth but increases the noise related to the finite phases of the PI. The proposed analytical formulas are validated against event-driven behavioral simulations of the CDR system including free-running oscillators as well as phase-locked loop (PLL) for clock generation.

Robust and reliable operation of high-speed serial interfaces (HSSI) in automotive environment is challenging. In this paper, we present the analysis and design of a 10Gbps receiver with 4-taps decision feedback equalizer (DFE) with 1-tap unrolled. A novel clock-and-data-recovery (CDR) algorithm is presented to consistently deal with the combined effect of Inter-Symbol Interference (ISI) and DFE on data transitions. The receiver, designed with a 28nm technology, consumes 2.05mW/Gbps and post-layout simulations are reported to show the advantage of the proposed architecture.

We report on the design of the physical layer of a high-speed serial interface for chip-to-chip communication, targeting low cost and ultra-low power (mW) IoT end-nodes. Two differential lanes (one pair per direction) are used to transmit/receive NRZ symbols at 1Gpbs with embedded clock. The energy-per-bit is lower than 1pJ/bit, thanks to a careful selection of termination impedance and voltage swing, tuned for moderate speed and short distance (2cm). The transceiver is designed to tolerate significant clock jitter, so that it can work with a half-rate clock shared with the rest of the chip, thereby minimizing area and power of supporting circuitry.