Functional verification accounts for a significant portion of the design effort in modern digital hardware development. As projects grow in complexity, maintaining and extending verification code becomes increasingly difficult, particularly in collaborative environments. This calls for a methodology that defines a clear structure and promotes reuse through modular, composable testbench components. In this paper, we present a Scala-based verification framework that adopts a structured approach to building modular and reusable testbenches, inspired by the Universal Verification Methodology (UVM). We analyze the core mechanisms through which UVM achieves modularity and reusability, and identify a minimal subset that provides equivalent functionality with reduced complexity. The result is a lightweight verification framework in Scala 3 using Verilator as a backend, which allows for simple unit-test-style testing as well as complex UVM-style testbench environments.

Speech Enhancement (SE) is essential for improving productivity in remote collaborative environments. Although deep learning models are highly effective at SE, their computational demands make them impractical for embedded systems. Furthermore, acoustic conditions can change significantly in terms of difficulty, whereas neural networks are usually static with regard to the amount of computation performed. To this end, we introduce Dynamic Channel Pruning to the audio domain for the first time and apply it to a custom convolutional architecture for SE. Our approach works by identifying unnecessary convolutional channels at runtime and saving computational resources by not computing the activations for these channels and retrieving their filters. When trained to only use 25% of channels, we save up to 32.4% of MACs while only causing a 0.32% drop in PESQ. Thus, DynCP offers a promising path toward deploying larger and more powerful SE solutions on resource-constrained devices.

Digital MicroFluidic Biochips (DMFBs) have emerged as platforms for automating biochemical protocols through precise droplet manipulation on miniaturized electrode arrays. Despite advancements in fluidic control, programming these systems remains a complex task, often requiring low-level, hardware-specific instructions. To address these limitations, we propose Liquid Computing, a conceptual shift that introduces a high-level, intention-driven programming model for DMFBs. We present a software framework that supports this vision, which includes a domain-specific language, a contamination-aware just-in-time compiler, and runtime execution with real-time sensor-driven dynamic protocol support. The solution is evaluated using a serial dilution protocol case study, targeting the BioWare cyber-fluidic platform. It successfully compiles contamination-constrained protocols, including edge cases with complex droplet interactions, in under one second.

Hearing aids and remote conference systems benefit from noise reduction. Current noise reduction approaches include machine-learning models that run on edge devices like hearing aids, AirPods, or headsets. Although not a safety-critical application, audio processing is a real-time application. We present a real-time enabled solution of speech enhancement with generation of$\mathbf{C}$code for embedded devices, executing on a real-time processor, and analyzing the worst-case execution time for that application. Using the Patmos processor and the Platin WCET analysis tool, we can guarantee that we process noise canceling within the given deadline.

Most digital hardware is described in hardware description languages, such as VHDL and (System)Verilog. These languages provide limited programming models for hardware construction despite receiving regular updates and extensions. Chisel defines itself as a hardware construction language, which means it shall permit more than the mere description of digital circuits. However, programmatic hardware generation is not new. Scripting languages like Perl generate VHDL or Verilog code from sources like Excel spreadsheets. Chisel, embedded in the general-purpose language Scala, lends itself to writing hardware generators in that language. We consider this Chisel-Scala ecosystem an ideal starting point for programming hardware generators and illustrate this point with examples using various programming models. We are confident that proven technologies from the software development world can be leveraged in the hardware design domain to improve hardware designers' productivity to build the next billion transistor chips.

Real-time embedded systems demand higher reliability than any other computer systems. These systems require special modeling paradigms to satisfy time constraints. This paper introduced a design method by combining T-CREST, a time-predictable multi-core hardware, with Lingua Franca, a coordination framework that generates deterministic time-predictable code. We executed a Lingua Franca piece of software on T-CREST platform and performed preliminary experiments demonstrating its correct functionality.

Digital microfluidic biochips exploit the electrowet-ting on dielectric effect to move and manipulate microliter-sized liquid droplets on a planar surface. This technology has the potential to automate and miniaturize biochemical processes, but reliability is often an issue. The droplets may get temporarily stuck or gas bubbles may impede their movement leading to a disruption of the process being executed. However, if the position and size of the droplets and bubbles are known at run-time, these undesired effects can be easily mitigated by the biochip control system. This paper presents an AI-based computer vision solution for real-time detection of droplets and bubbles in DMF biochips and its implementation that supports cloud-based deployment. The detection is based on the YOLOv5 framework in combination with custom pre and post-processing techniques. The YOLOv5 neural network is trained using our own data set consisting of 5115 images. The solution is able to detect droplets and bubbles with real-time speed and high accuracy and to differentiate between them even in the extreme case where bubbles coexist with transparent droplets.

Low-Power Wide Area Networks (LPWAN) offer long-range communication with low energy consumption, making them ideal for IoT applications powered by energy harvesting. However, unpredictable energy harvesting rates can lead to sub-optimal device operation. To tackle this, the intermittent computing paradigm has been proposed. In this paper, we explore the combination of intermittent computing and LPWANs by proposing four different communication solutions based on LoRa and designed to match common application scenarios and requirements. For the solutions, we also present experimental energy estimation models, which we evaluate against measurements.

Cyber-physical systems deployed in areas like automotive, avionics, or industrial control are often distributed systems. The operation of such systems requires coordinated execution of the individual tasks with bounded communication network latency to guarantee quality-of-control. Both the time for computing and communication needs to be bounded and statically analyzable. To provide deterministic communication between end-systems, real-time networks can use a variety of industrial Ethernet standards typically based on time-division scheduling and enforced by real-time enabled network switches. For the computation, end-systems need time-predictable processors where the worst-case execution time of the application tasks can be analyzed statically. This paper presents a time-predictable end-system with support for deterministic communication using the open-source processor Patmos. The proposed architecture is deployed in a TTEthernet network, and the protocol software stack is implemented, and the worst-case execution time is statically analyzed. The developed end-system is evaluated in an experimental network setup composed of six TTEthernet nodes that exchange periodic frames over a TTEthernet switch.

Distributed real-time systems need time-predictable computation and communication to facilitate static analysis of timing requirements and deadlines. This paper presents the implementation of a deterministic network protocol, TTEthernet, on the time-predictable Patmos processor. The implementation uses the existing Ethernet controller on the processor and we tested it with a TTEthernet system provided by TTTech Inc. Further testing showed that the controller could send time-triggered messages with bounded latency and a small jitter of approximately 4.5 us. We also provide worst-case execution time analysis of the network code, which demonstrates a time-predictable end-to-end solution. This work enables Patmos to communicate with other nodes in a deterministic way. Thus, extending the possible uses of Patmos.

In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading those accelerators that are needed at any given point in time. The DPR controllers provided by the FPGA vendors satisfy a wide range of requirements and rely on software to manage the reconfiguration. This approach may lead to slow reconfiguration and unpredictable timing. This paper presents an open-source DPR controller specially developed for hard real-time systems and prototyped in connection with the open-source multi-core platform for real-time applications T-CREST. The controller enables a processor to perform reconfiguration in a time-predictable manner and supports different operating modes. The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example is also presented with the scope of showing the reconfiguration features of the controller.

This paper presents an area-efficient time-division-multiplexing (TDM) network-on-chip (NoC) intended for use in a multicore platform for hard real-time systems. In such a platform, a mode change at the application level requires the tear-down and set-up of some virtual circuits without affecting the virtual circuits that persist across the mode change. Our NoC supports such reconfiguration in a very efficient way, using the same resources that are used for transmission of regular data. We evaluate the presented NoC in terms of worst-case reconfiguration time, hardware cost, and maximum operating frequency. The results show that the hardware cost for an FPGA implementation of our architecture is a factor of 2.2 to 3.9 times smaller than other NoCs with reconfiguration functionalities, and that the worst-case time for a reconfiguration is shorter or comparable to those NoCs.