In this paper, a novel two-dimensional (2-D) complex-valued spline interpolation lookup table (LUT) method is proposed to construct the cascaded digital predistortion (DPD) system. Three schemes, namely the 2-D complex-valued spline interpolation Wiener DPD (2D-CSPW), the 2-D complex-valued spline interpolation Hammerstein DPD (2D-CSPH), and the 2-D complex-valued spline interpolation Wiener-Hammerstein DPD (2D-CSPWH), are given for the DPD model construction, where the different serial orders of linear and nonlinear blocks are considered. The local mapping property achieved by the proposed approach can closely approximate the conventional polynomial model under strong power amplifier (PA) nonlinear conditions, involving only a few free parameters, which is promising for achieving real-time continuous nonlinear learning. The proposed DPD schemes have been extensively validated through different RF measurements, including those for highly nonlinear Doherty PA (DPA) and the load modulation balanced amplifier (LMBA), as well as the commercial PA. The results show that the proposed 2D-CSPWH achieves linear performance that closely approximates the conventional polynomial models, while reducing complexity by 90%, and the other two models also demonstrate optimal trade-offs between complexity and performance.

This article presents the design theory and implementation of a fully integrated octave-bandwidth monolithic microwave integrated circuit (MMIC) power amplifier (PA). While continuous-mode PA design theory provides a wide impedance design space for fundamental and harmonic frequencies, it faces limitations in octave-bandwidth scenarios, since the second harmonic frequency ($2f_{low}$) overlaps with the fundamental frequency ($f_{high}$). To address this challenge, we propose a novel design methodology that utilizes hybrid impedance selection based on the continuous-mode impedance trajectory at the fundamental frequency and the load-pull-based selection of feasible second harmonic impedance, addressing the octave-bandwidth challenge. A coupled-line-based matching network is introduced to simultaneously realize fundamental and harmonic impedance matching in an MMIC process. To validate the proposed approach, an octave-bandwidth gallium nitride (GaN) MMIC PA operating from 3.6-7.4 GHz (69.1% fractional bandwidth) is designed using a 0.25-$\mu m$GaN HEMT process. The fabricated PA achieves a measured drain efficiency (DE) of 40-54% from 3.6-7.4 GHz, with a peak output power of 35.5 dBm. When driven by a 100-MHz 5G New Radio (NR) 64 quadrature amplitude modulation (64-QAM) signal with a peak-to-average power ratio (PAPR) of 7.0 dB, the PA achieves an average DE of 27% at 4.0 GHz, and 25% at 5.0 GHz, respectively.

This paper presents a broadband Gallium Arsenide (GaAs) heterojunction bipolar transistor (HBT) Doherty power amplifier (DPA) that employs a lumped compensation network (LCN) and input phase correction technique for 5G applications. A LCN is utilized with an integrated impedance inverter to enhance output power back-off (OBO) efficiency across a wide frequency range. To mitigate the overdrive issue caused by the LCN under saturation, different input phase strategies are analyzed, and an on-chip coupler-based input phase correction network is introduced to maintain a constant phase difference between the carrier and peaking paths. The DPA is implemented using a 2$\mu $m GaAs HBT process and achieves broadband operation over 3.1-4.3 GHz with a fractional bandwidth exceeding 32%, covering the 5G n77 and n78 bands. Measurement results demonstrate a saturated output power of 32.73-33.77 dBm with a saturated power-added efficiency (PAE) of 39.54%-46.51%, a small-signal gain of 22.19-25.30 dB. At 6 dB OBO, the DPA maintains a PAE of 30.84%-34.95%. When tested with a 100 MHz bandwidth 64-QAM signal with 5.6 dB PAPR, the DPA achieves an average PAE of up to 34.3% and an adjacent channel power ratio (ACPR) better than -45.2 dBc after digital predistortion (DPD), demonstrating its potential for wideband 5G terminal applications.

Though Outphasing power amplifier (OPA) exhibits high efficiency across a wide dynamic power range, its frequency coverage is constrained, prompting novel design techniques to enable broadband or multi-band operation. This paper proposes a mode expansion methodology for OPAs that adopt a non-commensurate transmission line combiner (NCTLC). It is indicated in this paper that an NCTLC-based OPA has eight distinct operation modes by judiciously expanding the delta length and base length of the NCTLC, as well as reconfiguring the Outphasing angle. Theoretical analyses confirm that the performance advantages of the OPA can be preserved before and after mode expansion. It is precisely the multi-mode operation that enhances the design flexibility of NCTLC-based OPAs. Moreover, to efficiently design the NCTLC, a relationship between the back-off range of the OPA and the delta length of the NCTLC is established. For experimental validation, three prototypes are designed and fabricated using Wolfspeed CGH40010F devices. Among these, two single-band OPAs operate at 1.0 GHz and 1.2 GHz, and a dual-mode dual-band OPA operates at 1.96/2.48 GHz. The measurement results indicate that the saturation output power of all OPAs is greater than 43.1 dBm with drain efficiency (DE) of above 56%. In the meantime, the 6 dB back-off DEs of all OPAs exceed 50.5%.

This article presents a comprehensive theoretical analysis of the resilience demonstrated by the three-stage Doherty power amplifier (DPA) when operating under load mismatch conditions. Additionally, a novel reconfigurable three-stage DPA architecture is introduced, with the aim of enhancing resilience to load mismatch using exceptionally simple circuits and a one-dimensional (1D) control method. To validate the efficacy of this proposed architecture and control approach, a DPA prototype employing commercial gallium nitride (GaN) active devices has been designed and meticulously fabricated at 2 GHz. With a matched 50 Ω load, the fabricated three-stage DPA achieves a high-efficiency range of 9.5 dB with larger than 51% back-off drain efficiency (DE). Through the proposed 1D control, the DPA presents 47.0%–55.1% back-off efficiency with ≤ 2 dB power fluctuation at a 2:1 voltage standing wave ratio (VSWR) over a 360° phase span. When driven by a 20 MHz long-term evolution (LTE) signal with an 8 dB peak-to-average power ratio (PAPR), the DPA achieves 46.2%–53.9% average efficiency and better than −21 dBc adjacent channel power ratio (ACPR) without digital pre-distortion (DPD) under load mismatch conditions.

Hybrid beamforming reduces the hardware complexity of massive multiple-input multiple-output (MIMO) systems. In this architecture, one digital chain must drive all the power amplifiers (PAs) in the subarray. However, differences in PAs lead to poor linearization of shared digital pre-distortion (DPD). Based on circuit mechanisms and model simulations of PAs, this article identifies one reason for differences in PAs. Fluctuations in the manufacturing process lead to changes in the matching network of PAs, and the transmission characteristics of the matching network affect the nonlinear behavior of PAs. In order to reduce the network differences of PAs at the circuit level and improve the consistency of nonlinear behavior, this article proposes a consistency improvement scheme for MIMO power amplifier (PA) modules. The scheme uses the tuned network to correct the differences in the matching network. To validate the scheme, seven PAs from the same batch are corrected by the tuned network. Before and after the correction, the other PAs are linearized by the DPD signal of one PA. The measured bandwidths include 10 MHz and 40 MHz, and the measured power ranges from saturated average power to back-off of 9 dB. The results show that the PAs corrected by the tuned network have a better consistency. The linearization ability of the shared DPD one-drive-multiple is improved. The adjacent channel power ratio (ACPR) improvement reaches 14 dB.

There are lots of works on the bandwidth extension of symmetrical Doherty power amplifier (S-DPA) with a back-off range of 6 dB. However, it is still a challenge to simultaneously extend the bandwidth and back-off range of a S-DPA. This paper proposes a design methodology for extending the back-off range of a broadband S-DPA. Nonlinear current profile is introduced into the carrier sub-amplifier of the S-DPA. In this way, unequal power will be delivered to the load by the carrier and peaking amplifiers, leading to an extended high efficiency power range. More importantly, compared with previous works, the inversion ratio of the impedance inverter after the carrier transistor will be reduced in the proposed S-DPA, increasing the operation bandwidth. The combiner parameters of the proposed S-DPA with extended back-off range are derived based on a pre-determined nonlinear current profile. It is illustrated that the combiner parameters of the S-DPA can be expressed as a function of the combining load. Then, the bandwidth of the proposed S-DPA is subsequently analyzed under different combining load conditions. As a validation, a 1.4–2.2 GHz S-DPA with extended back-off range is implemented in this paper. Under a continuous-wave (CW) signal excitation, the fabricated S-DPA achieves a maximum output power of 40.2–43 dBm, a saturation drain efficiency (DE) of 56%–74% and a 9.0 dB back-off DE of 45%–52.5% over 1.4–2.2 GHz. Moreover, the fabricated S-DPA is also measured by the excitation of a 20 MHz modulated signal with a peak-to-average power ratio (PAPR) of 8.0 dB. The measured adjacent channel leakage ratios (ACLRs) of the fabricated S-DPA changes from −30.7 dBc to −21.1 dBc at the lower band and from −31.9 to −21.1 dBc at the upper band over 1.4–2.2 GHz when the average output power is 33.0 dBm.

The input impedance of the post-matching network (PMN) is configured as a complex value. The parameter solution space is determined based on the fundamental principles of the Doherty power amplifier (DPA), enabling the DPA to achieve high efficiency at the output power back-off (OBO). The parameter solution space comprises three variables: the phase parameter of the output matching network for the carrier power amplifier (carrier PA), the phase parameter of the output matching network for the peaking power amplifier (peaking PA), and the input impedance of PMN. These parameters are optimized to enable the DPA to achieve high efficiency at the OBO. In this paper, a one-to-one mapping relationship is established between the frequency and the parameter solution space, allowing for a precise optimization of the DPA across a broad frequency range. Leveraging this mapping relationship, an asymmetric DPA designed to operate over the 1.8–2.6 GHz frequency band is designed and fabricated, demonstrating the feasibility and effectiveness of the proposed approach. Under continuous wave excitation, the test results show that the drain efficiency (DE) is 42.7%–56.4% at 9.5 dB OBO and the saturated DE is 45.8%–71.1%. The saturated output power of this DPA is 46.9–48.8 dBm with a gain of 5.5–8.0 dB at saturation. A 20-MHz long-term-evolution modulated signal with a peak-to-average power ratio of 8 dB is also applied to the fabricated DPA at 1.8, 2.1, and 2.6 GHz. Under these conditions, at 8 dB OBO, the DPA shows an adjacent channel power ratio always lower than 48 dBc after digital pre-distortion linearization.

This article proposes a new phase compensation technique to expand the operating bandwidth of an asymmetric Doherty power amplifier (ADPA). Its operation principle is to increase the solution space of network parameters, thereby contributing to the broadband solvability of network parameters. The article provides a general method for solving network parameters in theory and numerical solutions for each network parameter. To verify the theory, a simple current source model simulates the load modulation process. The results show that this new compensation technique has consistent performance with the load modulation process of traditional ADPA at a similar parameter solution region. This technique can greatly expand the applicability of the network and allow for a more flexible design of ADPA. Furthermore, this theory was validated by designing a broadband ADPA of 1.7–2.7-GHz. The experimental results show that the saturation output power range is 46.9 dBm–48.5 dBm, with a saturation gain between 6 dB–9.3 dB and a corresponding saturation efficiency of 44%–69%. The efficiency is between 37%–65% at 6 dB back-off and 44%–52% at 9 dB back-off.

This article presents a theoretical analysis and circuit design for an enhanced dual-mode reciprocal Doherty power amplifier (DM-RDPA). To achieve bandwidth enhancement, an improved combining load design strategy is proposed, providing more accurate back-off impedance across a wider target bandwidth. Additionally, a sweeping analysis method is developed to determine optimal design parameters. The enhanced combining load design space of the proposed DM-RDPA is visualized, providing an intuitive view of the appropriate impedance solution space. To validate this enhanced DM-RDPA architecture and the corresponding design analysis method, a prototype PA was designed and fabricated using commercial GaN transistors. The implemented PA achieves two different Doherty operation bands: 0.95-1.9 GHz (66.7% fractional bandwidth) in Mode I and 0.67-0.93 GHz (32.5% fractional bandwidth) in Mode II. Drain efficiency of 47.3%-62.2% and 44.7%-62.1% is obtained by the fabricated DPA at 6 dB back-off in Mode I and Mode II, respectively. When driven by a 20 MHz modulated signal with 8 dB peak to average power ratio (PAPR), the fabricated DPA presents higher than 42% average efficiency in both Mode I and Mode II.

Though Outphasing power amplifiers (OPAs) can maintain high efficiency over a large dynamic range, their bandwidth should be further extended to satisfy the wireless communication systems. This paper presents a complex combining method for designing wideband OPAs. Complex combining impedance is adopted to compensate the frequency dispersion of the active load modulation in the OPA, leading to an extended bandwidth. It is illustrated for the first time that the load modulation trajectories of the OPA can be corrected over a wide bandwidth by elaborately designing the complex combining impedance. Furthermore, a comprehensive theoretical analysis is conducted on the transmission-line based combiner to derive the complex load impedance needed at different frequency points, recovering the back-off efficiency of a broadband OPA. As a proof of concept, a broadband OPA operating over 1.7-2.2 GHz is designed and fabricated. The experimental results show the fabricated OPA delivers a maximum output power of 43.1-44.3 dBm with a drain efficiency of 63.4%-78.4%. Meanwhile, a 6-dB back-off drain efficiency of 45.5%-70.4% can also be achieved by the fabricated OPA.

This article presents the methodology for designing triple-mode Doherty power amplifier (DPA) with multi-band operation and extended high efficiency range. It is illustrated that three different Doherty operation modes can be realized by simply re-setting the gate bias voltages while the DPA circuits keep unchanged. By employing a novel reciprocal gate bias DPA architecture, five operation bands have been achieved by the proposed DPA with larger than 9 dB high efficiency power range. The active load modulation process and theoretical performance of proposed DPA are analyzed in detail for each mode. For verification, a commercial GaN transistors-based DPA is designed and implemented with 1.76–1.96 GHz band in Mode I, 1.13–1.20/2.48–2.58 GHz bands in Mode II and 0.7–0.76/2.34–2.40 GHz bands in Mode III. The fabricated DPA achieves 7.0–10.5 dB saturation gain, 44.18–46.86 dBm peak output power and 41.9%–61.5% back-off efficiency. When stimulated by a 10 MHz long term evolution (LTE) modulation signal with 8.6 dB peaking-to-average ratio (PAPR), the adjacent channel power ratio (ACPR) of the fabricated DPA is better than −45 dBc after digital pre-distortion at 0.73, 1.18 and 1.85 GHz.

Doherty power amplifier (DPA) has shown great potentials in wireless communication systems. However, the output power and efficiency of a DPA are very susceptible to load mismatch. This paper presents the load mismatch analysis and compensation of coupler-based DPAs leveraging on dual-input and mode reconfiguration techniques. A comprehensive analysis, which takes voltage clipping into consideration, is conducted on a coupler-based dual-input DPA (CBDI-DPA) under load mismatch condition. It is illustrated that the parallel Doherty mode could recover the saturation and back-off drain efficiencies (DEs) for the load mismatch in the left and right half parts of the Smith chart, respectively. And the serial Doherty mode could recover the back-off and saturation DEs for the load mismatch in the left and right half parts of the Smith chart, respectively. As a validation, a CBDI-DPA operating at 2.4 GHz is fabricated and measured in this paper. Under the optimal load impedance condition, the fabricated CBDI-DPA delivers a saturation power of more than 43.5 dBm, a saturation DE of more than 70% and a 6 dB back-off DE of more than 60% in both the parallel and the serial Doherty modes. Meanwhile, the simulation and experimental results demonstrate the proposed method can recover the output power and efficiency of a DPA when the load mismatch is inside the 2:1 VSWR circle.

In this paper, an analytical design procedure for subnominal class$E_{M}$power amplifier (PA) is proposed. The main circuit only satisfies zero voltage switching (ZVS) and zero current switching (ZCS) conditions, which provide two extra design freedoms compared to the traditional class$E_{M}$PA. All the parameters in the circuit can be expressed as a function of the two design freedoms, and more selectable circuits with higher efficiency can be provided. Meanwhile, the design freedoms can also be applied to improve circuit performance by selecting suitable values. To validate the analytical process, two subnominal class$E_{M}$circuits are fabricated and measured with specific design freedoms at the operating frequency 2 MHz. The obtained output power for the two designs are 5.92 W and 13.45 W, and the efficiency can reach 96.1% and 97.3%, respectively. Compared to the traditional class$E_{M}$PA, the transistor peak voltages of the main and auxiliary circuits in the first design can be reduced by 10% and 27%, and the transistor peak voltage of the auxiliary circuit in the second design is reduced by 25%, which demonstrates that the subnominal operation can be well applied for decreasing the transistor voltage stress. The experimental results show the validity of the presented theoretical analysis.