This paper presents an event-based split-CNN architecture (ESCA) for running time-critical vision applications with comparatively less memory footprint while consuming low power. ESCA has a dedicated hardware architecture and scheduling of on-chip memory buffering using a split-CNN that reduces memory requirements by splitting the feature maps into small patches and independently executes them. The model emulates the concepts of the biological vision system to obtain possible events from each patch. We save energy and time by processing only the patches with possible events. The data-level parallelism is employed with a deep pipeline strategy that accelerates the system. We implement the design in the Virtex UltraScale+ FPGA at 320 MHz. Simulation results show that the architecture obtains significant speedup while power-saving depends on each image patch's features.

This paper presents the MeXT-SE (Multiprocessor Exploration Tool with Security Extension), an FPGAbased MPSoC development tool capable of generating platformindependent MPSoCs with enforced hardware access control mechanism from a high-level abstraction.

Convolutional Neural Networks have been adopted in a wide range of vision-based application domains in recent times, due to their success in enabling ubiquitous machine vision and intelligent decisions. However, the overwhelming computation demand of the convolution operations has somewhat limited their use in resource-constrained embedded platforms. This paper presents a pixel processing architecture to facilitate CNN inference near the image sensor. The architecture exploits the high bandwidth available at the sensor interface and incorporates an array of pixel processors to perform inference directly on the sensor device. The proposed design addresses problems related to the mapping of computations onto an array of pixel processors and introduces a suitable network structure for communication. The pixel processors are highly optimized to provide low latency and power for CNN applications. While designing the pixel processors, we focused on reducing redundancies using the concepts of biological vision systems. We prototype the model in a Virtex UltraScale FPGA and implement it in ASIC using the TSMC 90nm technology library. The results suggest that the proposed architecture significantly reduces dynamic power consumption and achieves high-speed up surpassing the computational capabilities of existing embedded processors.

Hardware accelerators are increasingly employed in conjunction with general-purpose processors to meet stringent performance constraints. In these heterogeneous systems, security has become a prime concern. In this article, we present a design approach to generate platform-independent secure multiprocessor systems-on-chip (MPSoC) from a high-level abstraction. The aim of this article is to simplify the implementation of MPSoC, while ensuring security. The proposed design flow starts with a set of abstract and concrete specifications of a system, provided by the user, and ends up generating a generic description of the appropriate hardware design by setting up the communication structure of different components. The resulting abstract architecture is further processed using the vendor tool-chain to generate the target platform's configuration. To enforce security, we proposed a distributed isolation framework for multilevel security, resource assess control including access to and from hardware accelerators. From a user specification, the security layer is transparently generated and security rules and requirements transparently enforced at run-time. Experimentation results show that our proposed tool can generate MPSoC designs capable of providing secure hardware execution with negligible execution overhead.

This paper presents a reconfigurable hierarchical hardware architecture at the pixel and region level for smart image sensors to accelerate machine vision applications. This architecture maintains hierarchical processing that begins at the pixel level. It reduces the computational burden on the sequential processor and accelerates the overall processing. There are three hierarchical layers, and each layer passes only the relevant information to the next layer by removing redundant information. This method facilitates the final processor to respond if there is an event in the scene. Identifying relevant information is complex, and we adapted different bio-inspired algorithms in the hierarchical layers to meet this purpose. Besides, these processors are made runtime reconfigurable to different applications, and it adds flexibility after fabrication. This hierarchical processing breaks the traditional sequential image processing and introduces parallelism for the machine vision applications. We evaluate the design in FPGA and achieve the GDSII file in ASIC platform at 800MHz. Simulation results show that the area overhead and power penalty for adding reconfiguration feature stay in an acceptable range. Besides, removing redundant information 84.01% and 96.91% dynamic power can be saved at the pixel-level and region-level, respectively.

This paper presents a reconfigurable hardware architecture of smart image sensors to speed up low-level image processing applications at the pixel level. For each pixel in the sensor plane, the design includes an activation module and a processor. The processor has a basic structure which is common to all applications and reconfigurable segments for specific applications. Visual cortex inspired computing, like, Predictive Coding in time is implemented in the activation module to remove temporal redundancy. The ASIC implementation shows the design saves up to 84.01% dynamic power and achieves 9x speedup at 800 MHz by accurate prediction.

Domain isolation enforcement is one of the challenging issues in software environments. To address this problem, NSA, in conjunction with the Secure Computing Corporation and the University of Utah, developed the open-source Flux Advanced Security Kernel (Flask), the mandatory access control (MAC) security architecture underlying major Operating Systems/Hypervisors widely deployed in cloud/desktop environments. In this work, we extend this security architecture to FPGA-based heterogeneous systems. Specifically, we explore the design and implementation of a security framework for controlled sharing of FPGA hardware modules in MAC-based OS/Hypervisor environments. The proposed design guarantees that hardware modules execute in the same security context as of the processes calling them by propagating the latter security policies expressed at the software level, down to the hardware. We prototype the proposed framework with SELinux and demonstrate its utility by evaluating trade-offs between security performance and execution overhead incurred by example applications. The preliminary results show our proposed framework provides isolation with an average of 0.6% worst case performance overhead.

This paper presents a CPU-FPGA heterogeneous system that provides hardware support for computer vision libraries to attain acceleration over image processing applications. The architecture achieves this improvement by staying completely transparent to the developer while providing necessary acceleration on conventional software designs.

In this paper, we present a new security framework which allows controlled sharing and isolated execution of mutually distrusted FPGA-accelerators in heterogeneous cloud systems. The proposed framework enables the accelerators running in FPGAs in cloud computers to transparently inherit at run-time, software security policies of the virtual machines processes calling them. This capability allows system security policies enforcement mechanism to propagate access control privilege boundaries expressed at the hypervisor level, down to individual FPGA-accelerators. Furthermore, we present a software/hardware prototype implementation of the proposed security framework, showing that it can easily be transparently integrated within the virtual machine software stacks that run in today's cloud-based systems. Experimentation results show our proposed framework provides secure hardware execution with negligible execution overhead on guest VMs applications.

The Hybrid Memory Cube (HMC) is representative of emerging architectures that integrate FPGAs with multichannel interconnected 3-D stacked memory, offering great potential for high bandwidth streaming applications. However, creating new hardware components that tap the full potential of the concurrent communications channels requires the structural understanding of the memory layout and interconnect configurations. In this paper, we present a new development framework aimed at removing the need for software programmers to understand the underlying physical architecture. The proposed framework automates the creation of hardware/software co-designs for computer vision applications in a transparent way to the developer. The development system dynamically detects function calls in software kernels and replaces those calls by a hardware wrapper function that exploits the HMCs memory hierarchy and multichannel interconnect with the FPGA. Results show our flow can exploit the 3-D stacked memory and concurrent communications channels to achieve speed-up with no need to tune the original software application to the memory hierarchy.

This paper explores the use of hardware sand-boxes, conceptually similar to software sandboxes, for secure integration of non-trusted IPs in systems-on-chip (SoC) designs. The goal of the hardware sandbox is to only allow permissible interactions between the IP and the rest of the system. The hardware sandbox design achieves this by exposing the IP interface to isolated virtual resources and checking IP signals' "correctness" at run-time. We evaluated the hardware sandbox through a real world design implementation. Our sandbox can detect a majority of Trust-Hub.org Trojan benchmarks with a negligible increase in resource overhead.