Demo Data from EDBT 2026 / reviewers in the wild / expert
Kibum Lee
dblp:185/5737
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 45% Energy-efficient computing · 34% Memory systems · 10% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs › FPGA reliability
FPGA fault tolerance |
0.3 | 1 | 2017 | Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM · IEEE Trans. Computers 2017 |
Energy-efficient computing
power gating |
0.3 | 1 | 2017 | Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM · IEEE Trans. Computers 2017 |
Reconfigurable computing and FPGAs
FPGA architecture |
0.1 | 1 | 2017 | Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM · IEEE Trans. Computers 2017 |
Integrated circuit design
monolithic integration |
0.1 | 1 | 2017 | Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM · IEEE Trans. Computers 2017 |
Memory systems › non-volatile memory
resistive memory |
0.1 | 1 | 2017 | Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM · IEEE Trans. Computers 2017 |
Methods — techniques the papers use, named apart from their topics
power gating · 0.3RRAM · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAMabstractThis paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. The proposed architecture does not require fine-grained fault location, and the error map is stored in non-volatile resistive memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the FPGA. The power gating scheme is implemented to save idle leakage power and fix hardware faults in the power network. Significant yield enhancement is expected using this architecture. The architecture has been verified in a test chip fabricated in 28nm technology. Redundancy operation is solely controlled by on chip fault locators which are HfO2-based resistive memories monolithically integrated after CMOS process. The maximum shift in performance is about 2 percent when the redundancy is engaged, and the power footprint is unaffected. Kibum Lee, S. Simon Wong |
IEEE Trans. Computers | 1 |