High-speed dynamic latch comparators are integral part of the state-of-the-art ADCs. This work presents a configurable dual-mode voltage comparator using a supply boosting technique. The power dissipation of the comparator is proportional to the square of the supply voltage. Hence, the comparator is configured to operate at a supply voltage of 0.9 V under normal operating conditions. During high-performance mode, when the input differential voltage is small, the supply voltage is boosted to 1.5 V, satisfying the power-delay trade-off. The architecture is designed and simulated in a 180-nm CMOS technology with a supply voltage of 0.9 V. The increased supply voltage of 1.5 V is generated internally using a switched capacitor technique. The power consumed at 0.9 V and 1.5 V is 0.4 mW and 1.29 mW, respectively. The simulated offset at ΔVIN= 1 mV in Mode = 0 and Mode = 1 turns out to be 4.05 mV and 3.14 mV respectively.

This paper presents an energy-efficient level shifter, which up-convert to 1.2 V from 0.3 V. The proposed architecture is based on single-stage differential cascode voltage switch logic (DCVSL) with multi-threshold transistors. A self-adapting pull-up (PU) network is used, which increases the switching speed and reduces energy consumption. To further improve the energy efficiency, a split-input inverting buffer with a higher threshold voltage is used in the output stage. The proposed design is implemented in 65 nm CMOS technology for$V_{DDL}=300\text{mV}$and$V_{DDH}=1.2$V. To up-convert from 0.3 V to 1.2 V, the proposed architecture has an average propagation delay of 11 ns and achieves 3.85 fJ of energy per transition at 1 MHz operating frequency.

This paper proposes a dual ramp, pulse position modulation analog-to-digital converter. A delay cell is proposed in this work, which converts the timing information into a thermometric code. The proposed architecture uses a dual ramp, which initiates the time to digital quantization from both Most Significant Bit (MSB) and Least Significant Bit (LSB) ends. It requires the use of two current sources at both the ends resulting in more symmetrical non-linearity behavior compared to single-ramp architecture, thus improving the INL of the ADC. This technique leads to an increase in the sampling frequency by a factor of 2. It is designed and implemented in a 65-nm CMOS technology with a supply voltage of 1-V. The proposed ADC achieves an effective number of bits of 4.49 bits at a sampling rate of 100 MHz.

Battery operated IoT sensor based applications require low energy interfacing circuits. This paper proposes an auxiliary circuit, which works on the principle of level-crossing sampling, for such energy aware applications. This circuit generates a power enable clock for the ADC, one of the most power hungry blocks in IoT sensor interfaces. The auxiliary circuit is designed and simulated at the transistor level using a standard 180-nm CMOS technology. The effectiveness of the proposed scheme is demonstrated by using a 5-bit flash ADC as a study case. The proposed auxiliary circuit consumes only 3.52% of the total power budget including the test ADC.