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Arun George

dblp:185/6917 · DBLP profile ↗
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4ranked-venue papers
1as first author
2since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 since 2021Computer networks · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Memory systems · 57% Storage systems · 43%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems
data placement
0.912025
Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs · EuroSys 2025
Memory systems › cache management › storage caching
flash cache management
0.912025
Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs · EuroSys 2025
Storage systems › flash and SSD › flash memory
flash storage
0.912025
Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs · EuroSys 2025
Operating systems › i/o › i/o subsystem
i/o path
0.812024
I/O Passthru: Upstreaming a flexible and efficient I/O Path in Linux · FAST 2024
Operating systems › kernel
linux kernel
0.812024
I/O Passthru: Upstreaming a flexible and efficient I/O Path in Linux · FAST 2024
Memory systems › non-volatile memory › persistent memory
byte-addressable persistent memory
0.412020
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces · HPCA 2020
Memory systems
memory interface
0.412020
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces · HPCA 2020
Memory systems
non-volatile memory
0.412020
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces · HPCA 2020
Memory systems › non-volatile memory › non-volatile main memory
NVDIMM
0.412020
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces · HPCA 2020
Storage systems › i/o architecture › i/o subsystem
storage i/o
0.212024
I/O Passthru: Upstreaming a flexible and efficient I/O Path in Linux · FAST 2024

Methods — techniques the papers use, named apart from their topics

garbage collection analysis · 0.9NVMe · 0.9system-wide mechanisms · 0.4asynchronous timing support · 0.4
YearPublicationVenuePosition
2025 Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs
abstract
NVMe Flash-based SSDs are widely deployed in data centers to cache working sets of large-scale web services. As data centers face increasing sustainability demands, such as reduced carbon emissions, efficient management of Flash overprovisioning and endurance has become crucial. Our analysis demonstrates that mixing data with different lifetimes on Flash blocks results in high device garbage collection costs, which either reduce device lifetime or necessitate host overprovisioning. Targeted data placement on Flash to minimize data intermixing and thus device write amplification shows promise for addressing this issue.
Michael Allison, Arun George, Javier González 0006, Dan Helmick, Roshan R. Nair, Vivek Shah 0001
EuroSys2
2024 I/O Passthru: Upstreaming a flexible and efficient I/O Path in Linux
Kanchan Joshi, Javier González 0006, Krishna Kanth Reddy, Arun George, Simon Andreas Frimann Lund, Jens Axboe
FAST6
2020 NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces
abstract
Currently, there are two representative non-volatile dual in-line memory module (NVDIMM) interfaces: a proprietary Intel DDR-T and the JEDEC NVDIMM-P, which are not supported by existing platforms. Adoption of new platform is costly and measuring its efficiency of migrating to the new platform is much more complex. This study is an alternative way of them—finding a new memory device that can be supported by all existing systems. In this paper, we propose an NVDIMM architecture with several system-wide mechanisms to allow the synchronous DDR4 memory interfaces to support non-deterministic (asynchronous) timing. The proposed memory architecture is implemented as a real device prototype, and also evaluated using synthetic and real workloads on an x86-64 server system.
Changmin Lee 0004, Wonjae Shin, Dae Jeong Kim, Yongjun Yu, Sung-Joon Kim, Taekyeong Ko, Deokho Seo, Kwanghee Lee, Seongho Choi 0002, Namhyung Kim, Vishak G, Arun George, Vishwas V, Donghun Lee 0001, Kang-Woo Choi, Changbin Song, Dohan Kim 0003, Insu Choi, Ilgyu Jung, Yong Ho Song, Jinman Han
HPCA13
2016 Efficiency analysis of M2M data collection networks using multipacket reception in frame-slotted ALOHA
abstract
We consider a Machine-to-Machine (M2M) network where a large number of user nodes (STAs) communicate with a Data Collector (DC). We consider the case where all the user nodes periodically transmit their data packets to the DC and the network is in saturation. Recently protocols based on Frame Slotted Aloha (FSA) have been shown to be suitable as MAC protocols for M2M data collection networks under saturated conditions. It can be shown that implementing Multi-Packet Reception (MPR) capability to the DC improves the performance of the FSA protocol. In this work we propose a Multi-Packet Reception (MPR) based FSA (MPR-FSA) protocol and study its performance. We derive the asymptotic limits of throughput, delay and energy efficiency based on MPR-FSA protocol. We also derive the limiting value of MPR (Klim) parameter for a given FSA based data collection network at which asymptotic performance is achieved. A mathematical model is proposed and the analytical values are validated using extensive simulations.
Arun George, T. G. Venkatesh 0001
WCNC1