One of the essential elements of computing is the memory element. Flip-flops form an integral part of a System-on-Chip (SoC) and consume most of the area on the die. To meet the high-speed performance demands by the data-intensive applications such as artificial intelligence, cloud computing, and machine learning, we propose to integrate memory with the logic to get built-in memory Logic circuits that operate based on the crosstalk computing logic. These circuits are called Crosstalk Built-in Memory Logic (CBML) circuits, which exploit the detrimental interconnect crosstalk and astutely turn this unwanted effect into a computing principle with embedded memory. By virtue of our novel CBML circuit technique, the logic is computed, and the result is stored intrinsically within these complex circuits. The stored values will be retained irrespective of the change in input until the next logic evaluation cycle. This neoteric embedding of memory in logic provides high-speed operation with a reduced number of transistors. In this article, we have manifested the built-in memory feature of the complex CBML circuits using 16 nanometer (nm) PTM models in HSPICE. Benchmarking is performed by comparing with the equivalent static CMOS circuits to compare the number of transistors, power, and performance. It is observed that the number of transistors consumed by CBML 4-bit Full-Adder (the key element prevalent in Arithmetic circuits, e.g., ALU, Counters) is up to 46% less, and performance is improved by 27% over the equivalent CMOS circuits. This circuit serves as an example of a large-scale CBML circuit. Also, the performance improvement achieved by other circuits such as 3-input AND and the CARRY logic is up to 60% along with a 40% reduction in the number of transistors. CBML circuits have the potential to pave the way for special high-speed macros with specifically engineered structures.

The functionality of polymorphic circuits can be altered using a control variable. Owing to the multifunctional embodiment in polymorphic circuits, they are helpful to reconfigure circuit behavior from the gate level to the system level, either on the fly or off-line. The polymorphic circuit approaches available in the literature are either based on custom nonlinear circuit designs or special emerging devices, such as ambipolar FET and configurable magnetic devices. While some of these approaches are inefficient in performance, the other approaches involve exotic devices. We have proposed a novel polymorphic circuit design approach based on crosstalk (CT) computing, where we leverage deterministic signal interference between nanometal lines for logic computation and reconfiguration. In this article, we elaborate upon the polymorphic circuit design in CT computing through mathematical formulation, which conveys the rationale to generalize and achieve a wide variety of polymorphic circuits, and then demonstrate a comprehensive list of polymorphic circuit designs. In addition, all circuits are characterized and benchmarked against CMOS circuit implementations to gauge the benefits. Finally, we compare the CT polymorphic circuit approach with other approaches in the literature and highlight its unique features and limitations. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to CT computing, which leads to benefits in the circuit power, performance, and area (PPA). Our circuit designs, simulation, and PPA characterization results show that the polymorphic CT circuits provide$3\times $improvement in transistor count,$2\times $improvement in switching energy, and$1.5\times $improvement in speed for polymorphic logic circuits. In the best-case, the transistor count reduction is$5\times $.

As 2-D CMOS reaches its fundamental scaling limits due to device, manufacturing, and interconnect bottleneck related constraints at the nanoscale, migration to 3-D provides a possible alternative to continue technology scaling in future. Toward that goal, several 3-D integration approaches with multi-die, multichip, and sequential layers stacking are pursued. However, these approaches only show incremental density benefits and exhibit new challenges, such as lack of thermal management, increasing cost, and reliability issues. In contrast to these, we proposed a radically different fabric concept, called stacked horizontal nanowire-based 3-D CMOS (SN3D), on a single die that can offer a paradigm shift in technology scaling as well as design. Using prefabricated and doped stacked horizontal nanowires as fundamental building blocks, the fabric is assembled using architected connectivity and insulation features. Innovations in circuit style for mapping to SN3D's physical framework, and bottom-up material filling-based manufacturing techniques are also central to our approach. In this paper, we detail, fabric's core constructs, logic circuits implementation in SN3D fabric, benchmarking methodology and results, and finally the manufacturing aspects. Our circuit analysis reveals tremendous benefits; for a 4-bit full adder design, SN3D shows 11×, 19%, 18%, and 6.7x, 8.69%, 9% benefits over state-of-art 2-D CMOS and transistor-level monolithic 3-D in terms of density, power, and performance, respectively. In addition, our step-by-step TCAD emulation of manufacturing flow establishes feasibility. If realized, the SN3D fabric can be transformative for the semiconductor industry.