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Sungmin Lim

dblp:186/1157 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1Human-computer interaction and ubiquitous computing · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 61% Processor architecture and microarchitecture · 30% Energy-efficient computing · 9%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
accelerator compilation
0.312018
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms · ISCA 2018
Hardware accelerators and domain-specific architectures
analog/mixed-signal accelerator
0.312018
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms · ISCA 2018
Processor architecture and microarchitecture
instruction set architecture
0.312018
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms · ISCA 2018
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.312018
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms · ISCA 2018
Energy-efficient computing › energy-quality tradeoff
energy-accuracy tradeoff
0.112018
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms · ISCA 2018

Methods — techniques the papers use, named apart from their topics

bayesian error modeling · 0.7analog/mixed-signal computing · 0.7
YearPublicationVenuePosition
2021 Work-in-Progress- - Is Virtual Reality Simulation Ineffective for Skill Acquisition Training?
abstract
The purpose of this work-in-progress paper is to examine the effect of levels of tactility with the presence and absence of a performance guide as formative feedback in an immersive virtual reality-based simulation (VRS). The experimental group will have four levels of tactile implementation, and the control group will have a non-virtual power tool. The experimental group will receive more specific feedback based on the data measured through virtual reality simulations. We will measure perceived task load, virtual presence, usability, and performance time and accuracy during training for all groups.
Museok Jeong, Sungmin Lim, Taehyeong Lim, Jeeheon Ryu
iLRN2
2018 PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms
abstract
Analog/mixed-signal machine learning (ML) accelerators exploit the unique computing capability of analog/mixed-signal circuits and inherent error tolerance of ML algorithms to obtain higher energy efficiencies than digital ML accelerators. Unfortunately, these analog/mixed-signal ML accelerators lack programmability, and even instruction set interfaces, to support diverse ML algorithms or to enable essential software control over the energy-vs-accuracy tradeoffs. We propose PROMISE, the first end-to-end design of a PROgrammable MIxed-Signal accElerator from Instruction Set Architecture (ISA) to high-level language compiler for acceleration of diverse ML algorithms. We first identify prevalent operations in widely-used ML algorithms and key constraints in supporting these operations for a programmable mixed-signal accelerator. Second, based on that analysis, we propose an ISA with a PROMISE architecture built with silicon-validated components for mixed-signal operations. Third, we develop a compiler that can take a ML algorithm described in a high-level programming language (Julia) and generate PROMISE code, with an IR design that is both language-neutral and abstracts away unnecessary hardware details. Fourth, we show how the compiler can map an application-level error tolerance specification for neural network applications down to low-level hardware parameters (swing voltages for each application Task) to minimize energy consumption. Our experiments show that PROMISE can accelerate diverse ML algorithms with energy efficiency competitive even with fixed-function digital ASICs for specific ML algorithms, and the compiler optimization achieves significant additional energy savings even for only 1% extra errors.
Prakalp Srivastava, Mingu Kang, Sujan K. Gonugondla, Sungmin Lim, Jungwook Choi, Vikram S. Adve, Nam Sung Kim, Naresh R. Shanbhag
ISCA4