With the advent of Machine Learning (ML), predictive EDA tools are becoming the next hot topic of research in the EDA community, and researchers are working on ML-based tools to predict the performance of the EDA tool. As the designs become complex, there is a need to start the design using higher levels of abstraction, such as High-Level Synthesis (HLS) tools in FPGA and SoC design flows. Quick prediction of performance-related parameters of the final design after the C-synthesis stage, can help in rapid design closure. Even though multiple papers exist in the domain of post routing performance prediction of HLS tools, there are no standard benchmarks available to compare the performance and accuracy of the predictive models. In this paper, we have presented MLSBench, a collection of around 5000 synthesizable designs written in C and C++. We provide a methodology to generate designs with various variations from a single design, which creates a potential for creating newer designs and enlarging the database in the future. This is followed by analysis, and validating the generated designs are indeed different. This allows designers to create generalized machine-learning-based models that are not overfitted to a small dataset. We also perform statistical analysis for measuring the design diversity by synthesizing them using Xilinx-Vivado HLS for Zynq 7000 device series.