Hardware accelerators are one promising solution to contend with the end of Dennard scaling and the slowdown of Moore's law. For mature workloads that are regular and have high compute per byte, hardening an application into one or more hardware modules is a standard approach. However, for some applications, we find that a programmable homogeneous architecture is preferable.

Specialized architecture combined with near- and subthreshold voltage circuits emerges as a promising candidate to improve the energy efficiency in performing complex computing kernels in a resource-constrained device. One of the critical challenges in such design is the large delay variability across process, voltage, and temperature (PVT) variations. The in situ error detection and correction (EDAC) technique can potentially handle such variations; however, since existing techniques have targeted von-Neumann architecture and nominal voltage circuits, it becomes nontrivial to apply them on near and subthreshold voltage accelerators, many of which do not base on the von-Neumann architecture. In particular, those accelerators often have no instruction, making it difficult to use the popular instruction-replay-based error correction. To tackle this challenge, in this paper, we propose a novel in situ EDAC technique that utilizes dynamic, temporarily, and spatially fine-grained body swapping for error correction without instruction replay. Using the proposed technique, we prototyped a spiking neural network (SNN) sorter in non-von-Neumann architecture. The prototyped chip can successfully remove the worst-case margin and, thus, achieve 49.3% higher energy efficiency and 35.6% higher throughput compared to the baseline that operates with the worst-case margin. The proposed technique incurs only 4.1% silicon area overhead and requires no additional supply voltage.

Programmable spatial architectures composed of ensembles of autonomous fixed-ISA processing elements offer a compelling design point between the flexibility of an FPGA and the compute density of a GPU or shared-memory many-core. The design regularity of spatial architectures demands examination of the processing element microarchitecture early in the design process to optimize overall efficiency.

This paper presents a design approach for improving energy-efficiency and throughput of parallel architectures in near- and subthreshold voltage circuits. The focus is to suppress leakage energy dissipation of the idle portions of circuits during active modes, which can allow us to wholly transform the throughput improvement from parallel architectures into energy savings via deep voltage scaling. We begin by investigating the efficacy of parallel and pipeline architectures in the near- and subthreshold circuits. The investigation reveals that active energy dissipation largely undermines the ability of deep voltage scaling to transform excessive throughput into energy savings. Techniques, such as power-gating switches (PGSs), can mitigate active-leakage power dissipation; however, the overhead for entering and exiting sleep modes can offset the energy savings provided by sleep mode, particularly if sleep time is fine grained for suppressing active leakage. Therefore, in this paper, we propose a PGS design technique, inspired by the so-called zigzag supercutoff CMOS, in order to optimize the overheads of mode transitions of PGS in near- and subthreshold circuits. The proposed technique enables to have circuits in sleep mode for as short as a single clock cycle with a negligible amount of energy and delay overheads. We apply our proposed design to parallel multiplier-based test circuits operating at near- and subthreshold voltages. Simulations show a significant improvement in energy-efficiency over baselines at the same throughput.