Xufeng Kou

dblp:186/2107 · DBLP profile ↗
← Back
5ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0002-8860-5105ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 since 2021Applied, interdisciplinary, general and emerging computing · 1
YearPublicationVenuePosition
2026 Fully Parallel Ising Machine with MRAM based p-bit Probabilistic Simulated Annealing
Tianhao Chen, Tianqu Hu, Shan Yao, Chengshuo Yu, Tianxiao Nie, Xufeng Kou
ISCAS6
2026 Generic Cryogenic VLSI Design Flow and Optimization Strategies for Energy-Efficient Computing
Yumeng Yuan, Kagan Irez, Xufeng Kou
ISCAS6
2024 A 12-bit 75 MS/s Asynchronous SAR ADC with Gain-Boosting Dynamic Comparator
abstract
This paper proposes a successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring a gain-boosting dynamic comparator design and a low-delay SAR logic. The proposed comparator incorporates positive feedback in the pre-amplifier, which enables high gain during the integration phase, thereby improving energy efficiency. Meanwhile, to ensure sufficient settling time for the internal capacitive digital-to-analog converter (CDAC), an asynchronous SAR logic with low logic delay in the SAR logic loop is implemented. Accordingly, a prototype ADC is manufactured using 28-nm CMOS technology, which achieves a power consumption of 860 μW at a 75 MHz sampling frequency. Moreover, the measured signal-to-noise and distortion ratio (SNDR) of the prototype at the Nyquist frequency is 60.9 dB, which translates to a Walden figure of merit (FOMW) of 12.7 fJ/conversion-step.
Renhe Chen, Yongqi Hu, Hao Xu 0005, Xufeng Kou
ISCAS5
2022 Cryo-CMOS Model-Enabled 8-Bit Current Steering DAC Design for Quantum Computing
abstract
This paper reports an 8-bit current steering-type cryogenic digital-to-analog converter (DAC) module using HLMC 40nm low-power (40LP) technology for fast qubit initialization in quantum computers. Based on the generic design platform generated from our cryo-CMOS compact model, we optimize the circuit to ensure its correct function with temperature-insensitive non-linearity. Benefiting from the integration of the nA-range on-chip current reference and appropriate gate sizing, a low power consumption of 13.8 $\mu$W under the mixed power supply of l.1 V/1.8V is achieved in this DAC design with an active area of 0.0074 mm2. With the realization of the stable output range of 6 mV and fast sampling rate of 140 MS/s at low temperatures, our cryo-DAC is able to manipulate the physical qubit, hence laying a solid foundation for practical large-scale quantum computing applications.
Yongqi Hu, Renhe Chen, Zhidong Tang, Chengwei Cao, Weican Wu, Shoumian Chen, Yuhang Zhao 0002, Liujiang Yu, Ganbing Shang, ShaoJian Hu, Xufeng Kou
ISCAS14
2016 Electric-Field Control of Spin-Orbit Interaction for Low-Power Spintronics
abstract
Spintronics is regarded as a promising solution for resolving the major challenging issues related to the scaling of Si-based complementary metal–oxide–semiconductor (CMOS) technology as it offers the advantages of combing the spin and charge degrees of freedom. After decades of progress, the quintessence to achieve practical low-dissipation applications lies in the ability to manipulate magnetic states by electric field via several different physical mechanisms. Among them, the emergence of the spin-orbit coupling engineering has been shown to dramatically reduce energy dissipation and improve the performance as well as to multiply spintronic device possibilities and functionalities for a new generation of ultralow-power nonvolatile spintronic systems. This article provides a review of the current development including fundamental physics and experimental implementations of electric-field-controlled ferromagnetism in dilute magnetic semiconductors, voltage control of magnetic anisotropy, spin-orbit-torque-assisted magnetization switching, and antiferromagnetic (AFM) material-based spin-orbitronic systems. We provide an assessment in terms of scaling of energy, speed, and size. Finally, we offer an outlook of electric-field-controlled spintronic applications, particularly in view of their integration with CMOS to form hybrid spintronic circuits.
Kang L. Wang, Xufeng Kou, Pramey Upadhyaya, Yabin Fan, Qiming Shao, Guoqiang Yu, Pedram Khalili Amiri
Proc. IEEE2