Convolutional Neural Networks (CNNs) have become dominant in object detection tasks. However, off-chip data traffic, primarily from intermediate feature maps, remains a major performance bottleneck in CNN accelerators. This paper proposes a deep learning accelerator for YOLOv7-tiny with the following features: 1) A Shortcut-Aware Layer Fusion method that reduces off-chip feature map traffic by 32%. 2) A Multi-Bank Memory Control Scheme that efficiently manages all feature map data in one unified on-chip buffer, eliminating unnecessary data copying and improving the utilization of buffer resources. The design is implemented in TSMC 28 nm HPC+ process and occupies 2.19 mm2. The proposed accelerator achieves an energy efficiency of 3.0 TOPS/W and processes 640×640 input images at 34.5 FPS.

This paper presents a low power and high throughput multi-framed pipelined LDPC decoder architecture based on a novel partial syndrome-based dynamic decoding (PSDD) approach. The proposed PSDD can reduce clock cycle to allow the LDPC decoder to be implemented with better energy efficiency. We propose a high throughput sorting method and implement the LDPC decoder with a pipelined multi-frame VLSI architecture. The implementation results for the IEEE 802.15.3d Thz standard shows that the proposed design has a coding gain of 10−8at the specified SNR of 18.1 dB with 16 QAM modulation. Furthermore, the proposed design can achieve a throughput rate of 128.5 Gbps with the 16nm FinFET CMOS process, respectively.